VHDL modeling and simulation for a digital target imaging architecture for multiple large targets generation

Abstract : The subject of this thesis is to model and verify the correctness of the architecture of the Digital Image Synthesizer (DIS) The DIS, a system-on-a-chip, is especially useful as a counter-targeting repeater. It synthesizes the characteristic echo signature of a pre- selected target. The VHDL description of the DIS architecture was exported from Tanner S-Edit, modified, and simulated. Different software oriented verification approaches were researched and a White-box approach to functional verification was adopted. An algorithm based on the hardware functionality was developed to compare expected and simulated results, Initially, the architecture of one Range Bin Modulator was exported. Modifications to the VHDL source code included modeling of the behavior of the N-FET and P-FET transistors as well as Ground and Vdd (the voltages connected to the drains of the FETs). It also included renaming of entities to comply with VHDL naming conventions. Simulation results were compared to manual calculations and Matlab programs to verify the architecture. The procedure was repeated for the architecture of an Eight-Range Bin Modulator with equally successful results. VHDL was then used to create a super class of a 32-Range Bin Modulator. Test vectors developed in Matlab were used to yet again verify correct functionality.

[1]  Jörg Bormann,et al.  Model Checking in Industrial Hardware Design , 1995, 32nd Design Automation Conference.

[2]  Hantao Zhang,et al.  Formal semantics of VHDL for verification of circuit designs , 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

[3]  Laurence Pierre,et al.  Formal verification of VHDL descriptions in the Prevail environment , 1992, IEEE Design & Test of Computers.

[4]  D. Beatty,et al.  An integrated environment for HDL verification , 1995, Proceedings. 1995 IEEE International Verilog HDL Conference.

[5]  Sudhakar Yalamanchili.  Introductory VHDL: From Simulation to Synthesis , 2000 .

[6]  C. Eisner,et al.  RuleBase: an industry-oriented formal verification tool , 1996, 33rd Design Automation Conference Proceedings, 1996.

[7]  Janick Bergeron,et al.  Writing Testbenches: Functional Verification of HDL Models , 2000 .

[8]  D. Deharbe,et al.  Formal verification of VHDL: the model checker CV , 1998, Proceedings. XI Brazilian Symposium on Integrated Circuit Design (Cat. No.98EX216).

[9]  D. J. Fouts,et al.  An All-Digital Image Synthesizer for Countering High-Resolution Imaging Radars , 2000 .

[10]  D. J. Fouts,et al.  A single-chip false target radar image generator for countering wideband imaging radars , 2002, IEEE J. Solid State Circuits.