A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits

The hardware implementation of AES algorithm as an asynchronous circuit has a reduced leakage of information through side-channels and enjoys high performance and low power. Dual-rail data encoding and return-to-spacer protocol are used to avoid hazards, including data-dependent glitches, and in order to make switching activity data-independent (constant). The implementation uses a coarse pipeline architecture which is different from traditional micropipelines. The pipeline stages are complex and have built-in controllers implemented as chains of David cells (special kind of latches), whose behaviour is similar to fine-grain pipelines. A highly balanced security latch is designed. The design is partly speed-independent; in a few places it uses well localised and justified relative timing assumptions. The security properties of the system are evaluated by extensive simulation and by counting switching activity.