High-Level Synthesis Of Inverse Quantization And Transform Block For HEVC Decoder On FPGA

This paper presents an efficient High-level synthesis (HLS) hardware design to implement the Inverse Quantization and Transform (IQ/IT) for a High Efficiency Video Coding (HEVC) decoder. Using Xilinx Vivado HLS tool, different directives are applied to the IQ/IT C code to select the optimized hardware architecture in terms of area and clock cycles. This architecture is implemented in a SW/HW context for verification. In fact, it is connected to ARM Cortex-A9 processor using AXI stream interface and integrated on Xilinx Zynq ZC702 platform. Therefore, the experimental results show that the SW/HW design can only decode 240p@15fps with a gain of 8% in throughput and 74% in power consumption compared to SW implementation.