论文信息 - Electrostatic Discharge Robustness of Si Nanowire Field-Effect Transistors

Electrostatic Discharge Robustness of Si Nanowire Field-Effect Transistors

Electrostatic discharge (ESD) performance of N-type double-gated Si nanowire (NW) thin-film transistors is investigated, for the first time, using the transmission line pulsing technique. The ESD robustness of these devices depends on the NW dimension, number of channels, plasma treatment, and layout topology. The failure currents, leakage currents, and on-state resistances are characterized, and possible ESD protection applications of these devices for future NW field-effect-transistor-based integrated circuits are also discussed.

[1] M. Okushima,et al. Layout technique to alleviate soft failure for short pitch multi finger ESD protection devices , 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

[2] C. Duvvury,et al. The impact of technology scaling on ESD robustness and protection circuit design , 1995 .

[3] Huang-Chung Cheng,et al. The effects of NH 3 plasma passivation on polysilicon thin-film transistors , 1995 .

[4] Christian Russ. ESD issues in advanced CMOS bulk and FinFET technologies: Processing, protection devices and circuit strategies , 2008, Microelectron. Reliab..

[5] Performance Enhancement in Double-Gated Poly-Si Nanowire Transistors With Reduced Nanowire Channel Thickness , 2009, IEEE Electron Device Letters.

[6] Fabrication and Characterization of Poly-Si Nanowire Devices with Performance Enhancement Techniques , 2007, 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

[7] S.C. Rustagi,et al. High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices , 2006, IEEE Electron Device Letters.

[8] B. Ryu,et al. Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires , 2006, 2006 International Electron Devices Meeting.