Design and tolerance analysis of a 5.7 GHz chip-size microstrip antenna on high resistivity silicon

This paper reports the FEM model, design, fabrication and characterization of a square patch antenna built on high-resistivity silicon (HRS) for operation at 5.7 GHz [Figure 1]. The HRS high dielectric constant of 11.7 leads to antenna size reduction enabling the antenna direct coupling on a chip with RF electronics, which offers potential of low cost, low profile and simplified assembly. The metal patch was made using a 2-μm layer of aluminium and has an area of 7.7x7.6 mm. The operating frequency and bandwidth were obtained from reflection measurements and are shown in Figure 2. The efficiency of 18.6% was measured using the Wheeler cap method [Figure 2]. The antenna operates at a center frequency of 5.705 GHz, providing a –10 dB return loss bandwidth of 90 MHz. Far-field gain patterns measurements were done using an anechoic chamber and results compared simulations [Figure 3]. The measured gain is ~0.3 dB. Also, FEM analysis was used to study the tolerance of the substrate thickness, substrate resistivity, oxide thickness and metal conductivity in order to predict the antenna behavior [Figure 4]. It was observed that varying the substrate thickness from 500 μm to 550 μm and oxide thickness from 1 μm to 10 μm the operating frequency changes from around 5.7 GHz to 5.85 GHz. Changing the substrate conductivity from 0.02 S/m to 0.05 S/m we found that efficiency changes from 19.6 % to 30.1 %. A wireless link between two prototypes was established and a power of –50 dBm was received when they were placed one meter apart and the transmitting antenna was fed with 0 dBm.