Modeling Advanced FET Technology in a Compact Model

The need for meeting the expectations of continuing the enhancement of CMOS performance and density has inspired the introduction of new materials into the classical single-gate bulk MOSFET and the development of nonclassical multigate transistors at an accelerated rate. There is a strong need to understand and model the associated new physics and electrical behavior to ensure widespread very-large-scale-integration circuit applications of new technologies. This paper presents some of the efforts toward the modeling of new technologies for bulk MOSFETs and multigate transistors. A holistic model for mobility enhancement through process-induced stress and a dynamic behavior model for high-k transistors have been developed to capture some of the new effects and new materials in the bulk MOSFET. A new analytical model is also presented for the fundamentally new device structure-FinFET

[1]  L. Pantisano,et al.  Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics , 2003, IEEE Electron Device Letters.

[2]  Xuemei Xi Ali M. Niknejad Chenming Hu Mohan V. Dunga A Holistic Model for Mobility Enhancement through Process-Induced Stress , 2005, 2005 IEEE Conference on Electron Devices and Solid-State Circuits.

[3]  X. Garros,et al.  Characterization and modeling of hysteresis phenomena in high K dielectrics , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[4]  Tsu-Jae King,et al.  Impact of oxygen vacancies on high-/spl kappa/ gate stack engineering , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[5]  J.C. Lee,et al.  High-k dielectrics and MOSFET characteristics , 2003, IEEE International Electron Devices Meeting 2003.

[6]  Daniel Foty,et al.  Perspectives on scaling theory and CMOS technology - understanding the past, present, and future , 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

[7]  Yuan Taur,et al.  Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs , 2001 .

[8]  H. Wong,et al.  CMOS scaling into the nanometer regime , 1997, Proc. IEEE.

[9]  A. De Keersgieter,et al.  Layout impact on the performance of a locally strained PMOSFET , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[10]  A. Oishi,et al.  Scalability of strained silicon CMOSFET and high drive current enhancement in the 40 nm gate length technology , 2003, IEEE International Electron Devices Meeting 2003.

[11]  Yuan Taur,et al.  Device scaling limits of Si MOSFETs and their application dependencies , 2001, Proc. IEEE.

[12]  J. Brews A charge-sheet model of the MOSFET , 1978 .

[13]  D. Frank,et al.  Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[14]  Charles S. Smith Piezoresistance Effect in Germanium and Silicon , 1954 .

[15]  C. Auth,et al.  Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[16]  M. Nishihara,et al.  Nonlinearity of the piezoresistance effect of p-type silicon diffused layers , 1982, IEEE Transactions on Electron Devices.

[17]  M. Jurczak,et al.  Experimental and comparative investigation of low and high field transport in substrate- and process-induced strained nanoscaled MOSFETs , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[18]  C. Hu,et al.  FinFET-a self-aligned double-gate MOSFET scalable to 20 nm , 2000 .

[19]  Bin Yu,et al.  FinFET scaling to 10 nm gate length , 2002, Digest. International Electron Devices Meeting,.

[20]  Ali M. Niknejad,et al.  Dynamic Behavior Model for High-k MOSFETs , 2006 .

[21]  G. Bersuker,et al.  Intrinsic characteristics of high-k devices and implications of fast transient charging effects (FTCE) , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..