High-Performance Adder Circuit Generators in Parameterized Structural VHDL

In ASIC design, arithmetic components are usually selected from tooland technology-dependent libraries providing very limited flexibility and choice of circuit structures. With the possibility of parameterized structural circuit descriptions at the gate-level in VHDL, versatile circuit generators can be implemented which are highly independent of tool platforms and design technologies. This enables the realization of a universal and comprehensive library of efficient arithmetic components in form of a collection of synthesizable VHDL code entities. In a first step, high-performance adder generators were implemented using this method. Additionally, valuable experience was gained with respect to the implementation of circuit generators using parameterized structural VHDL. This work was funded by MICROSWISS (Microelectronics Program of the Swiss Government).