Cost Effective and High Performance 28nm FPGA with New Disruptive Silicon-Less Interconnect Technology (SLIT)

This paper introduces the first comprehensive demonstration of new disruptive innovation technology comprising multiple Xilinx patent-pending innovations for highly cost effective and high performance Xilinx FPGA, which is so called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex® -7 2000T FPGA product. Chip-to-Wafer stacking, wafer level flux cleaning, micro-bump underfilling, mold encapsulation are newly developed. Of all technology elements, both full silicon etching with high etch selectivity to dielectric/fast etch rate and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. In order to manage the wafer warpage after full Si removal, a couple of knobs are identifie...

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