Building expressive, area-efficient coherence directories
暂无分享,去创建一个
Peng Liu | Michael C. Huang | Qi Hu | Lei Fang | Guofan Jiang | Peng Liu | Michael C. Huang | Qi Hu | Lei Fang | G. Jiang
[1] Andreas Moshovos,et al. A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).
[2] Dong-Sheng Wang,et al. Hierarchical Cache Directory for CMP , 2010, Journal of Computer Science and Technology.
[3] Anoop Gupta,et al. Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes , 1990, ICPP.
[4] Per Stenström,et al. The Scalable Tree Protocol-a cache coherence approach for large-scale multiprocessors , 1992, [1992] Proceedings of the Fourth IEEE Symposium on Parallel and Distributed Processing.
[5] José González,et al. A new scalable directory architecture for large-scale multiprocessors , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.
[6] Dhiraj K. Pradhan,et al. Two economical directory schemes for large-scale cache coherent multiprocessors , 1991, CARN.
[7] Kai Li,et al. The PARSEC benchmark suite: Characterization and architectural implications , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).
[8] Michael C. Huang,et al. DDCache: Decoupled and Delegable Cache Data and Metadata , 2009, 2009 18th International Conference on Parallel Architectures and Compilation Techniques.
[9] Andreas Moshovos. RegionScout: exploiting coarse grain sharing in snoop-based coherence , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).
[10] Mark D. Hill,et al. An evaluation of directory protocols for medium-scale shared-memory multiprocessors , 1994, ICS '94.
[11] Antonio Robles,et al. Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks , 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).
[12] Kyu Ho Park,et al. Segment directory enhancing the limited directory cache coherence schemes , 1999, Proceedings 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing. IPPS/SPDP 1999.
[13] Jr. Richard Thomas Simoni,et al. Cache coherence directories for scalable multiprocessors , 1992 .
[14] Michael C. Huang,et al. Improving support for locality and fine-grain sharing in chip multiprocessors , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).
[15] Vijayalakshmi Srinivasan,et al. SPATL: Honey, I Shrunk the Coherence Directory , 2011, 2011 International Conference on Parallel Architectures and Compilation Techniques.
[16] Laxmi N. Bhuyan,et al. Design of an Adaptive Cache Coherence Protocol for Large Scale Multiprocessors , 1992, IEEE Trans. Parallel Distributed Syst..
[17] Stein Gjessing,et al. Distributed-directory scheme: scalable coherent interface , 1990, Computer.
[18] Paul Feautrier,et al. A New Solution to Coherence Problems in Multicache Systems , 1978, IEEE Transactions on Computers.
[19] Christoforos E. Kozyrakis,et al. SCD: A scalable coherence directory with flexible sharer set encoding , 2012, IEEE International Symposium on High-Performance Comp Architecture.
[20] D. Lenoski,et al. The SGI Origin: A ccnuma Highly Scalable Server , 1997, Conference Proceedings. The 24th Annual International Symposium on Computer Architecture.
[21] Kevin M. Lepak,et al. Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor , 2010, IEEE Micro.
[22] Vijayalakshmi Srinivasan,et al. A Tagless Coherence Directory , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[23] Deborah A. Wallach. PHD: A Hierarchical Cache Coherent Protocol , 1992 .
[24] Anoop Gupta,et al. The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.
[25] Guoying Chen. SLID - A Cost-Effektive and Scalable Limited-Directory Scheme for Cache Coherence , 1993, PARLE.
[26] Ronak Singhal,et al. Inside Intel® Core microarchitecture (Nehalem) , 2008, 2008 IEEE Hot Chips 20 Symposium (HCS).
[27] Mark D. Hill,et al. Virtual hierarchies to support server consolidation , 2007, ISCA '07.
[28] Anoop Gupta,et al. Analysis of cache invalidation patterns in multiprocessors , 1989, ASPLOS III.
[29] R. Govindarajan,et al. Emulating Optimal Replacement with a Shepherd Cache , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).
[30] Mark Horowitz,et al. An evaluation of directory schemes for cache coherence , 1998, ISCA '98.
[31] Balaram Sinharoy,et al. POWER7: IBM's next generation server processor , 2010, 2009 IEEE Hot Chips 21 Symposium (HCS).
[32] Mohammad Alisafaee. Spatiotemporal Coherence Tracking , 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.
[33] Margaret Martonosi,et al. Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).
[34] Sandhya Dwarkadas,et al. SPACE: Sharing pattern-based directory coherence for multicore scalability , 2010, 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT).
[35] Anant Agarwal,et al. LimitLESS directories: A scalable cache coherence scheme , 1991, ASPLOS IV.
[36] A.R. Newton,et al. An empirical evaluation of two memory-efficient directory methods , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.
[37] Laxmi N. Bhuyan,et al. An efficient hybrid cache coherence protocol for shared memory multiprocessors , 1996, Proceedings of the 1996 ICPP Workshop on Challenges for Parallel Processing.
[38] Andrew B. Kahng,et al. ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.
[39] Todd M. Austin,et al. The SimpleScalar tool set, version 2.0 , 1997, CARN.
[40] N. Gura,et al. UltraSPARC T2: A highly-treaded, power-efficient, SPARC SOC , 2007, 2007 IEEE Asian Solid-State Circuits Conference.
[41] Mikko H. Lipasti,et al. Improving multiprocessor performance with coarse-grain coherence tracking , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).