A module selection algorithm for high-level synthesis

A heuristic approach to the module selection problem in high-level synthesis is presented. In contrast to the common assumption made by most high-level synthesis systems, which consider one available resource for each type of operation, the authors assume that several resources with different delays and areas are available in a functional-block library. The proposed algorithm solves the scheduling, resource sharing, and module selection problems at the same time to achieve a circuit structure with near minimal area under a given overall latency constraint. Following the presentation of the algorithm, experimental results are reported.<<ETX>>