Multi-layer bus minimization for SoC

The deployment of multiple processing elements such as a microprocessor or a Digital Signal Processor in embedded systems often results in significant communication overheads. The challenge lies in resolving the communication cost minimization problem, while simultaneously satisfying the timing constraints of job executions. In this paper, we explore bus-layer minimization problems by first identifying factors that contribute to the NP-hardness of these problems. Existing proposed algorithms and NP-hard problems are then identified and elucidated. A simulated annealing algorithm is proposed and compared with heuristics-based algorithms to provide further insights for system designers. Lastly, a series of extensive simulations is carried out and a case study is presented to show comparisons among different approaches and workloads.

[1]  Giovanni De Micheli,et al.  Hardware-software cosynthesis for digital systems , 1993, IEEE Design & Test of Computers.

[2]  Koichi Nishida,et al.  A C-based synthesis system, Bach, and its application , 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

[3]  Chi-Sheng Shih,et al.  On-Chip Bus Architecture Optimization for Multi-core SoC Systems , 2007, SEUS.

[4]  Ville Leppänen,et al.  Resource allocation methodology for the segmented bus platform , 2005, Proceedings 2005 IEEE International SOC Conference.

[5]  S. G. Zaky,et al.  Communication performance in multiple-bus systems , 1988, IEEE Trans. Computers.

[6]  Gaetano Borriello,et al.  The Chinook hardware/software co-synthesis system , 1995 .

[7]  Dr. Zbigniew Michalewicz,et al.  How to Solve It: Modern Heuristics , 2004 .

[8]  T. C. Hu.  Parallel Sequencing and Assembly Line Problems , 1961 .

[9]  Georg Färber,et al.  An Off-Line Variable-Size Bin Packing for EDF , 2006 .

[10]  Koichi Nishida,et al.  A C-based synthesis system, Bach, and its application (invited talk) , 2001, ASP-DAC '01.

[11]  Edwin Hsing-Mean Sha,et al.  Bus minimization and scheduling of multi-chip systems , 1995, Proceedings. Fifth Great Lakes Symposium on VLSI.

[12]  Wayne H. Wolf,et al.  Performance estimation for real-time distributed embedded systems , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[13]  Wayne H. Wolf,et al.  TGFF: task graphs for free , 1998, Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98).

[14]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[15]  Paolo Crippa,et al.  System-Level Power Analysis Methodology Applied to the AMBA AHB Bus , 2003, DATE.

[16]  Luca Benini,et al.  Simultaneous memory and bus partitioning for SoC architectures , 2005, Proceedings 2005 IEEE International SOC Conference.

[17]  M. A. Cleveland,et al.  The Problem With Critical Path Scheduling Algorithms , 1996 .

[18]  Hyuk-Jae Lee,et al.  A new multi-channel on-chip-bus architecture for system-on-chips , 2004, IEEE International SOC Conference, 2004. Proceedings..

[19]  Diederik Verkest,et al.  System-level interconnect architecture exploration for custom memory organizations , 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).

[20]  Takayuki Sasaki,et al.  A practical approach for bus architecture optimization at transaction level , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[21]  Petru Eles,et al.  Scheduling of conditional process graphs for the synthesis of embedded systems , 1998, DATE.