Technology mapping for k/m-macrocell based FPGAs

In this paper, we study the technology mapping problem for a novel FPGA architecture that is based on <italic>k</italic>-input single-output PLA-like cells, or, <italic>k/m</italic>-macrocells. Each cell in this architecture can implement a single output function of up to <italic>k</italic> inputs and up to <italic>m</italic> product terms. We develop a very efficient technology mapping algorithm, k_m_flow, for this new type of architecture. The experiment results show our algorithm can achieve depth-optimality in practically all cases. Furthermore it is shown that the <italic>k/m</italic>-macrocell based FPGAs are practically equivalent to the traditional <italic>k</italic>-LUT based FPGAs with only a relatively small number of product terms (<italic>m≤k</italic> + <italic>3</italic>). We also investigate thetotal are and delay of <italic>k/m</italic>-macrocell based FPGAs on various benchmarks to compare it with commonly used 4-LUT based FPGAs. The experimental result shows <italic>k/m</italic>-macrocell based FPGAs can outperform 4-LUT based FPGAs in terms of both delay and area after placement and routing by VPR.

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