Design exploration of IGZO diode based VCMA array design for Storage Class Memory Applications

This paper presents the Design Technology Co-optimization (DTCO) study of the 1-diode 1- Voltage controlled magnetic anisotropy (1D-1VCMA) stack, which functions as Storage Class Memory (SCM) to bridge the gap between DRAM and flash memory. The dual requirement of low sneak current and high non-linearity for bidirectional selectors in 1S-1R crossbar memories is extremely challenging to achieve practically. Moreover, the IR drop due to parasitic resistance (RPAR) results in significant degradation in the voltage across the memory element (ME) and causes write disturbance for the 1S-1R crossbar. 1D-1VCMA solves the above-mentioned issues by having low write current (Iw), (thus reducing IR drop) and increasing the number of DINs /DOUTs to improve energy/bit. Sneak current and non-linearity are also significantly improved due of the diode selector. Based on our VCMA and IGZO diode technology data and an extensive DTCO, we are able to achieve a write energy consumption of 880fJ/bit (at a delay of 40.5ns and VDD of 2V), and read energy consumption of 414fJ/bit (at a read delay of 39ns), thus showing a significant improvement over similar SCMs.

[1]  K. Sankaran,et al.  Demonstration of a Free-layer Developed With Atomistic Simulations Enabling BEOL Compatible VCMA-MRAM with a Coefficient ≥100fJ/Vm , 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

[2]  G. Kar,et al.  High-density SOT-MRAM technology and design specifications for the embedded domain at 5nm node , 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

[3]  E. Beyne,et al.  System exploration and technology demonstration of 3D Wafer-to-Wafer integrated STT-MRAM based caches for advanced Mobile SoCs , 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

[4]  G. Groeseneken,et al.  Deterministic and field-free voltage-controlled MRAM for high performance and low power applications , 2020, 2020 IEEE Symposium on VLSI Technology.

[5]  C. Carabasse,et al.  Crosspoint Memory Arrays: Principle, Strengths and Challenges , 2020, 2020 IEEE International Memory Workshop (IMW).

[6]  S. H. Sharifi,et al.  Sub-µm a-IGZO, Fully integrated, Process improved, Vertical diode for Crosspoint arrays , 2020, 2020 IEEE International Memory Workshop (IMW).

[7]  Y. Huai,et al.  Threshold switching selector and 1S1R integration development for 3D cross-point STT-MRAM , 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

[8]  P. Narayanan,et al.  Access devices for 3D crosspoint memorya) , 2014 .

[9]  J. G. Alzate,et al.  Diode-MTJ Crossbar Memory Cell Using Voltage-Induced Unipolar Switching for High-Density MRAM , 2013, IEEE Electron Device Letters.

[10]  J. G. Alzate,et al.  Voltage-induced switching of nanoscale magnetic tunnel junctions , 2012, 2012 International Electron Devices Meeting.

[11]  Onur Mutlu,et al.  Architecting phase change memory as a scalable dram alternative , 2009, ISCA '09.