Improved parallel cascade control structure for time delay processes

Parallel cascade control structure is commonly used in the operation of process industries to reject disturbances that have a rapid effect on a secondary measured state, before the primary measured variable is affected. The investigations on PID tuning rules for SISO systems are many; however the literature about synthesis methods for designing and tuning cascade control structures appears to be rather limited. In this paper, the usefulness of a new dead time compensator scheme in the outer loop of the parallel cascade control structure is investigated. The robust control performances can be obtained using this method. Simulation results show the usefulness and superiority of the proposed control method over the existing ones.