Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography

Self-aligned double patterning (SADP) lithography is a leading technology for 10nm node Metal layer fabrication. In order to achieve successful decomposition, SADP-compliant design becomes a necessity. Spacer-Is-Dielectric (SID) is the most popular flavor of SADP with higher flexibility in design. This paper makes a careful study on the challenges for SID-compliant detailed routing and proposes a graph model to capture the decomposition violations and SID intrinsic residue issues. Then a negotiated congestion based scheme is adopted to solve the overall routing problem. The proposed SID-compliant detailed routing algorithm simultaneously assigns colors to the routed wires, which provides valuable information guiding SID decomposition. In addition, if one pin has multiple candidate locations, the optimal one will be automatically determined during detailed routing. The decomposability of the conflict-free routing layers produced by our detailed router is verified by a commercial SADP decomposition tool.

[1]  Li Lin,et al.  Design compliance for spacer is dielectric (SID) patterning , 2012, Advanced Lithography.

[2]  James P. Shiely,et al.  Enhanced spacer-is-dielectric (sid) decomposition flow with model-based verification , 2013, Advanced Lithography.

[3]  Kun Yuan,et al.  Layout Decomposition for Triple Patterning Lithography , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Larry McMurchie.  Chapter 17 – Pathfinder: A Negotiation-Based Performance-Driven Router for FPGAs , 2008 .

[5]  David Z. Pan,et al.  Layout decomposition of self-aligned double patterning for 2D random logic patterning , 2011, Advanced Lithography.

[6]  Yuelin Du,et al.  A polynomial time exact algorithm for self-aligned double patterning layout decomposition , 2012, ISPD '12.

[7]  Yuelin Du,et al.  Self-aligned double patterning decomposition for overlay minimization and hot spot detection , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[8]  J. Andres Torres,et al.  Self-aligned double-patterning (SADP) friendly detailed routing , 2011, Advanced Lithography.

[9]  Yuelin Du,et al.  Effective decomposition algorithm for self-aligned double patterning lithography , 2011, Advanced Lithography.

[10]  Andrew B. Kahng,et al.  Layout decomposition for double patterning lithography , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[11]  Andrew B. Kahng,et al.  Layout Decomposition Approaches for Double Patterning Lithography , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  David Z. Pan,et al.  Flexible self-aligned double patterning aware detailed routing with prescribed layout planning , 2012, ISPD '12.

[13]  T. Knight,et al.  Pathfinder : A Negotiation-Based Performance-Driven Router for FPGAs , 2012 .

[14]  Yunfei Deng,et al.  Decomposition strategies for self-aligned double patterning , 2010, Advanced Lithography.