A performance-driven analog-to-digital converter module generator

A performance-driven analog-to-digital converter (ADC) module generator, CADICS, which generates ADC netlists and layouts from a set of specifications is presented. The module generator consists of a circuit synthesis which is based on a hierarchical optimization approach and a layout synthesis which was implemented using a hierarchical layout procedure. At each level of performance, silicon area and power dissipation are optimized so that they are comparable with manual design. The synthesis is built around a one-bit-per-cycle algorithmic A/D converter architecture. Layouts of 6-b, 8-b, and 10-b ADCs generated by CADICS in a 2- mu m CMOS process are shown.<<ETX>>

[1]  M. Degrauwe,et al.  A Micropower CMOS-Instrumentation Amplifier , 1985, IEEE Journal of Solid-State Circuits.

[2]  Alberto L. Sangiovanni-Vincentelli,et al.  CADICS-cyclic analog-to-digital converter synthesis , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[3]  Bernhard E. Boser,et al.  The Design of Sigma-Delta Modulation Analog-to-Digit a 1 Converters , 2004 .

[4]  Larry J. Stockmeyer,et al.  Optimal Orientations of Cells in Slicing Floorplan Designs , 1984, Inf. Control..

[5]  A. Sangiovanni-Vincentelli,et al.  Constraint-based channel routing for analog and mixed analog/digital circuits , 1990, ICCAD 1990.

[6]  Rob A. Rutenbar,et al.  A Prototype Framework for Knowledge-Based Analog Circuit Synthesis , 1987, DAC 1987.

[7]  M. W. Hauser,et al.  MOS ADC-filter combination that does not require precision analog components , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[8]  Alberto L. Sangiovanni-Vincentelli,et al.  A routing methodology for analog integrated circuits , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[9]  M. Townsend,et al.  An NMOS Microprocessor for Analog Signal Processing , 1980 .