A 4GS/s, 8.45 ENOB and 5.7fJ/conversion, digital assisted, sampling system in 45nm CMOS SOI

A 4GS/s sampling system achieved 8.45-ENOB linearity with 5.7fJ/conversion energy efficiency at 1V power supply and its gain can be adjusted in a digital manner. The measured IIP3 and IIP2 are 17.7dBm and 40dBm respectively. The ENOB of the sampler shows no degradation up to Nyquist frequency. An integrated phase rotator allows digital clock delay and duty cycle adjustment with sub-picosecond resolution. The sampling system tracks and settles in 1/4UI (62.5ps). Realized in a 45nm SOI CMOS the active area of the sampler is only 0.2×0.2mm2.

[1]  Jesper Steensgaard,et al.  Bootstrapped low-voltage analog switches , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[2]  Rui Paulo Martins,et al.  A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[3]  S. Shahramian,et al.  A 40-G samples/sec track & hold amplifier in 0.18/spl mu/m SiGe BiCMOS technology , 2005, IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05..

[4]  A. Abidi,et al.  A 3 . 3V 12b 50-MS / s A / D Converter in 0 . 6-m CMOS with over 80-dB SFDR , 2000 .

[5]  P. R. Gray,et al.  A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter , 1999, IEEE J. Solid State Circuits.

[6]  Sorin P. Voinigescu,et al.  A 40-GSamples/Sec Track & Hold Amplifier in 0.18µm SiGe BiCMOS Technology , 2005 .

[7]  P.E. Allen,et al.  A 1.2 GSample/s Double-Switching CMOS THA With ${- }$62 dB THD , 2009, IEEE Journal of Solid-State Circuits.

[8]  A.A. Abidi,et al.  A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with over 80-dB SFDR , 2000, IEEE Journal of Solid-State Circuits.

[9]  Mohamed Dessouky,et al.  Very low-voltage digital-audio /spl Delta//spl Sigma/ modulator with 88-dB dynamic range using local switch bootstrapping , 2001 .

[10]  Paul R. Gray,et al.  A 1.5 V, 10-bit, 14 MS/s CMOS pipeline analog-to-digital converter , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[11]  C. Andre T. Salama,et al.  Track-and-hold and comparator for a 12.5GS/s, 8bit ADC , 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.