A state-based modeling approach for fast performance evaluation of embedded system architectures

Abstract models are means to assist system architects in the evaluation process of hardware/software architectures and then to cope with the still increasing complexity of embedded systems. Efficient methods are necessary to correctly model system architectures and to make possible early performance evaluation and fast exploration of the design space. In this paper, we present the use of a specific modeling approach to improve evaluation of non-functional properties of embedded systems. The contribution is about a computation method defined to improve modeling of properties used for assessment of architecture performances. This method favors creation of abstract transaction level models and leads to significantly reducing simulation time but still preserving accuracy of results. The benefits of the proposed approach for evaluation of performances of system architectures are highlighted through analysis of two specific case studies.

[1]  Frank Ghenassia Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems , 2010 .

[2]  Gunar Schirner,et al.  Quantitative analysis of the speed/accuracy trade-off in transaction level modeling , 2008, TECS.

[3]  Andy D. Pimentel,et al.  A systematic approach to exploring embedded system architectures at multiple abstraction levels , 2006, IEEE Transactions on Computers.

[4]  Wolfgang Rosenstiel,et al.  Integrated requirement evaluation of non-functional system-on-chip properties , 2008, 2008 Forum on Specification, Verification and Design Languages.

[5]  Ralf Irmer,et al.  3G evolution , 2008, IEEE Microwave Magazine.

[6]  C. Carbonelli,et al.  On 3G LTE Terminal Implementation - Standard, Algorithms, Complexities and Challenges , 2008, 2008 International Wireless Communications and Mobile Computing Conference.

[7]  Jean Paul Calvez Embedded real-time systems: a specification and design methodology , 1993 .

[8]  Frank Ghenassia,et al.  Transaction Level Modeling with SystemC , 2005 .

[9]  Masato Edahiro,et al.  FIDES: An advanced chip multiprocessor platform for secure next generation mobile terminals , 2008, ACM Trans. Embed. Comput. Syst..

[10]  Sandeep K. Shukla,et al.  Automated concurrency re-assignment in high level system models for efficient system-level simulation , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[11]  Daniel Gajski,et al.  Transaction level modeling: an overview , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

[12]  Andreas Gerstlauer,et al.  System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design , 2008, EURASIP J. Embed. Syst..

[13]  Matthias Gries,et al.  Methods for evaluating and covering the design space during early design development , 2004, Integr..

[14]  Florence Maraninchi,et al.  A Method for the Efficient Development of Timed and Untimed Transaction-Level Models of Systems-on-Chip , 2008, 2008 Design, Automation and Test in Europe.

[15]  Yang Qu,et al.  Combining UML2 Application and SystemC Platform Modelling for Performance Evaluation of Real-Time Embedded Systems , 2008, EURASIP J. Embed. Syst..

[16]  Timo Hämäläinen,et al.  Performance Evaluation of UML2-Modeled Embedded Streaming Applications with System-Level Simulation , 2009, EURASIP J. Embed. Syst..

[17]  Christian Haubelt,et al.  A SystemC-Based Design Methodology for Digital Signal Processing Systems , 2007, EURASIP J. Embed. Syst..

[18]  Erik Dahlman,et al.  3G Evolution: HSPA and LTE for Mobile Broadband , 2007 .

[19]  G. G. Stokes "J." , 1890, The New Yale Book of Quotations.

[20]  Roberto Passerone,et al.  A Platform-Based Taxonomy for ESL Design , 2006, IEEE Design & Test of Computers.