Analysis of operation of ring LFSR used for testing of unidirectional interleaved interconnections

The paper presents analysis of operation of a specific ring LFSR register that can be used to test a network of n interleaved interconnections between modules of digital circuits. This register is a distinctive option of the already known BIST structure referred to as CSTP. When the test is carried out for unidirectional interconnections, the CSTP becomes a linear register and the lines under test make up feedback lines of that register. Due to the fact that layout of these lines looks like the ‘X’ letter that register is referred to as the XR-LFSR. The fault-free XR-LFSR can be reflected by an automaton with the G0 cyclic state diagram and each physical defect f transforms that G0 state diagram into another state diagram Gf ≠ G0. To verify its efficiency for detection of faults the method of state diagram identification was applied. The same authors in previous studies dedicated to bus-type connections observed that the sequence of m states of G0 state diagram, where m > 2n and n > 16, is sufficient to detect a substantial number of static and delay faults for such buses. The present paper comprises the observation that any randomly selected state of the state diagram for the XR-LFSR belongs, with a pretty high level of probability, exceeding 70%, to the cycle with the maximum length cmax. It was also spotted that for n>16 more than 98,4% of all structures lead to sufficiently long cycles cmax > 1000. The both observations confirmed usefulness of XR-LFSRs for testing of unidirectional connections.

[1]  Hu Chuan-Gan,et al.  On The Shift Register Sequences , 2004 .

[2]  Abhijit Chatterjee,et al.  Switching activity generation with automated BIST synthesis forperformance testing of interconnects , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  N. Jacobson,et al.  Basic Algebra II , 1989 .

[4]  Benoit Nadeau-Dostie,et al.  An embedded technique for at-speed interconnect testing , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[5]  A. Hlawiczka,et al.  Application of modified ring LFSRs for interconnect faults detection , 2008, 2008 15th International Conference on Mixed Design of Integrated Circuits and Systems.

[6]  Mehrdad Nourani,et al.  Testing interconnects for noise and skew in gigahertz SoCs , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[7]  Krzysztof Gucwa,et al.  Interconnect Faults Identification and Localization Using Modified Ring LFSRs , 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.

[8]  N. Jacobson,et al.  Basic Algebra I , 1976 .

[9]  Rodham E. Tulloss,et al.  The Test Access Port and Boundary Scan Architecture , 1990 .

[10]  公庄 庸三 Basic Algebra = 代数学入門 , 2002 .

[11]  M. Lipson,et al.  Schaum's Outline of Theory and Problems of Linear Algebra , 1968 .

[12]  Arthur D. Friedman,et al.  Fault detection in digital circuits , 1971 .

[13]  J. Koeter,et al.  Interconnect testing using BIST embedded in IEEE 1149.1 designs , 1991, [1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit.

[14]  Ieee Standard Test Access Port and Boundary-scan Architecture Ieee-sa Standards Board , 2001 .

[15]  Krzysztof Gucwa,et al.  Effective BIST for crosstalk faults in interconnects , 2009, 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

[16]  Andrzej Krasniewski,et al.  Circular self-test path: a low-cost BIST technique for VLSI circuits , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Artur Jutman,et al.  At-speed on-chip diagnosis of board-level interconnect faults , 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

[18]  Chauchin Su,et al.  Configuration free SoC interconnect BIST methodology , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).