A digit-recurrence square root implementation for field programmable gate arrays

Creating efficient arithmetic processors requires a pairing of high speed arithmetic algorithms with optimal mapping strategies for a given technology. The authors propose bit reduction as key to an efficient pairing process for lookup table based field programmable gate arrays (FPGAs). Bit reduction simplifies the functions defining the original algorithm, thus permitting a mapping to fewer blocks and reducing the overall throughput delay. A mapping of a digit-recurrence square root algorithm to the Xilinx XC4010 FPGA illustrates the bit reduction process.<<ETX>>

[1]  Tomás Lang,et al.  On-the-Fly Conversion of Redundant into Conventional Representations , 1987, IEEE Transactions on Computers.

[2]  Milos D. Ercegovac,et al.  Mapping division algorithms to field programmable gate arrays , 1992, [1992] Conference Record of the Twenty-Sixth Asilomar Conference on Signals, Systems & Computers.

[3]  Charles E. Leiserson,et al.  Optimizing Synchronous Circuitry by Retiming (Preliminary Version) , 1983 .

[4]  G. De Micheli,et al.  Logic transformations for synchronous logic synthesis , 1990, Twenty-Third Annual Hawaii International Conference on System Sciences.

[5]  Jean Vuillemin,et al.  Programmable Active Memories: A Performance Assessment , 1992, Heinz Nixdorf Symposium.

[6]  Mark Shand,et al.  Hardware speedups in long integer multiplication , 1991, SIGARCH Comput. Archit. News.

[7]  Jean Vuillemin,et al.  Introduction to programmable active memories , 1990 .

[8]  Milos D. Ercegovac,et al.  On digit-recurrence division implementations for field programmable gate arrays , 1993, Proceedings of IEEE 11th Symposium on Computer Arithmetic.

[9]  Reza Hashemian,et al.  Square Rooting Algorithms for Integer and Floatingg-Point Numbers , 1990, IEEE Trans. Computers.

[10]  John Paul Shen,et al.  Flexible processors: a promising application-specific processor design approach , 1988, MICRO 1988.

[11]  A. Sangiovanni-Vincentelli,et al.  Retiming and resynthesis: optimizing sequential networks with combinational techniques , 1990, Twenty-Third Annual Hawaii International Conference on System Sciences.

[12]  Tomás Lang,et al.  Module to Perform Multiplication, Division, and Square Root in Systolic Arrays for Matrix Computations , 1991, J. Parallel Distributed Comput..

[13]  Tomás Lang,et al.  A division algorithm with prediction of quotient digits , 1985, 1985 IEEE 7th Symposium on Computer Arithmetic (ARITH).