Home Platform PNX 8550 System Chip

Philips has adopted a modular manufacturing test strategy for its SOCs that are part of the Nexperia Home Platform. The on-chip infrastructure that enables modular testing consists of wrappers and Test Access Mechanisms (TAMs). Optimizing that infrastructure minimizes the test application time and helps to fit the test data into the ATE vector memory. This paper presents the test architecture design for the chiplet-based PNX8550, the most complex Nexperia SOC designed to date. Significant savings in test time and TAM wires could be obtained with the help of TR-ARCHITECT, an in-house tool for automated design of SOC test architectures.

[1]  Erik Jan Marinissen,et al.  A structured and scalable mechanism for test access to embedded reusable cores , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[2]  E.J. Marinissen,et al.  Scan chain design for test time reduction in core-based ICs , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[3]  Yervant Zorian,et al.  Testing Embedded-Core-Based System Chips , 1999, Computer.

[4]  Bart Vermeulen,et al.  Test and debug strategy of the PNX8525 Nexperia/sup TM/ digital video platform system chip , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[5]  Santanu Dutta,et al.  Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems , 2001, IEEE Des. Test Comput..

[6]  Yervant Zorian,et al.  On IEEE P1500's Standard for Embedded Core Test , 2002, J. Electron. Test..

[7]  Erik Jan Marinissen,et al.  Effective and efficient test architecture design for SOCs , 2002, Proceedings. International Test Conference.

[8]  Erik Jan Marinissen,et al.  A set of benchmarks for modular testing of SOCs , 2002, Proceedings. International Test Conference.

[9]  Erik Jan Marinissen,et al.  Layout-driven SOC test architecture design for test time and wire length minimization , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[10]  Erik Jan Marinissen,et al.  SOC test architecture design for efficient utilization of test bandwidth , 2003, TODE.

[11]  Erik Jan Marinissen,et al.  Control-aware test architecture design for modular SOC testing , 2003, The Eighth IEEE European Test Workshop, 2003. Proceedings..