Partitioning routing area into zones with distinct pins

Topological routing has gained importance in state-of-the-art layout synthesis. This paper poses the problem of partitioning the routing area of a given placement into a minimum set of zones such that in each zone, no two pins belong to the same net. Thus, topological routing can be completed among the zones whereas within a zone the only wires are from a pin to the boundary of the zone. Hence, such partitioning may accelerate routing by reducing the problem size. The related problem of identifying a zone with maximum number of distinct pins is also considered here. Both problems are observed to be NP-hard. A genetic algorithm for the first one and a greedy heuristic for the second problem are proposed. Experimental results are observed to be near optimal in most of the cases.

[1]  Naveed A. Sherwani,et al.  Algorithms for VLSI Physical Design Automation , 1999, Springer US.

[2]  Andrew B. Kahng,et al.  Recent directions in netlist partitioning: a survey , 1995, Integr..

[3]  David S. Johnson,et al.  Computers and In stractability: A Guide to the Theory of NP-Completeness. W. H Freeman, San Fran , 1979 .

[4]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[5]  Susmita Sur-Kolay,et al.  Topological routing amidst polygonal obstacles , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

[6]  Jason Cong,et al.  A Parallel Bottom-up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design , 1993, 30th ACM/IEEE Design Automation Conference.

[7]  Malgorzata Marek-Sadowska,et al.  Circuit clustering using graph coloring , 1999, ISPD '99.

[8]  Andrew B. Kahng,et al.  Recent developments in netlist partitioning: a survey , 1995 .

[9]  Maurizio Rebaudengo,et al.  GALLO: a genetic algorithm for floorplan area optimization , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Michael Ian Shamos,et al.  Computational geometry: an introduction , 1985 .

[11]  Susmita Sur-Kolay,et al.  Area(number)-balanced hierarchy of staircase channels with minimum crossing nets , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[12]  I. Koren,et al.  Optimal aspect ratios of building blocks in VLSI , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..