Survey of Self-Adaptive NoCs with Energy-Efficiency and Dependability
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[1] Gert Jervan,et al. System-Level Design of NoC-Based Dependable Embedded Systems , 2011 .
[2] Li-Shiuan Peh,et al. Leakage power modeling and optimization in interconnection networks , 2003, ISLPED '03.
[3] Li Shang,et al. Dynamic voltage scaling with links for power optimization of interconnection networks , 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..
[4] Kees van Berkel,et al. Multi-core for mobile phones , 2009, DATE.
[5] Trevor Mudge,et al. Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..
[6] Salim Hariri,et al. Autonomic Computing: An Overview , 2004, UPP.
[7] Carl E. Landwehr,et al. Basic concepts and taxonomy of dependable and secure computing , 2004, IEEE Transactions on Dependable and Secure Computing.
[8] Kees G. W. Goossens,et al. A Monitoring-Aware Network-on-Chip Design Flow , 2006, DSD.
[9] Henry Hoffmann,et al. Enabling technologies for self-aware adaptive systems , 2010, 2010 NASA/ESA Conference on Adaptive Hardware and Systems.
[10] Hermann Kopetz,et al. The Complexity Challenge in Embedded System Design , 2008, 2008 11th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC).
[11] Saurabh Dighe,et al. A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling , 2011, IEEE Journal of Solid-State Circuits.
[12] Giovanni De Micheli,et al. A robust self-calibrating transmission scheme for on-chip networks , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[13] Stephen B. Furber,et al. Chain: A Delay-Insensitive Chip Area Interconnect , 2002, IEEE Micro.
[14] Hideharu Amano,et al. Run-time power gating of on-chip routers using look-ahead routing , 2008, 2008 Asia and South Pacific Design Automation Conference.
[15] Hannu Tenhunen,et al. Hierarchical agent monitoring design approach towards self-aware parallel systems-on-chip , 2010, TECS.
[16] Ahmed Louri,et al. Adaptive Channel Buffers in On-Chip Interconnection Networks— A Power and Performance Analysis , 2008, IEEE Transactions on Computers.
[17] Paul Ampadu,et al. Transient and Permanent Error Co-management Method for Reliable Networks-on-Chip , 2010, 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip.
[18] Li-Shiuan Peh,et al. Exploring the Design Space of Self-Regulating Power-Aware On/Off Interconnection Networks , 2007, IEEE Transactions on Parallel and Distributed Systems.
[19] Ladan Tahvildari,et al. Self-adaptive software: Landscape and research challenges , 2009, TAAS.
[20] Paul Ampadu,et al. Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[21] Davide Bertozzi,et al. Variation tolerant NoC design by means of self-calibrating links , 2008, 2008 Design, Automation and Test in Europe.
[22] Axel Jantsch,et al. Adaptive Power Management for the On-Chip Communication Network , 2006, 9th EUROMICRO Conference on Digital System Design (DSD'06).
[23] Amit Kumar Singh,et al. Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms , 2010, J. Syst. Archit..
[24] Ran Ginosar,et al. Data synchronization issues in GALS SoCs , 2004, 10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings..
[25] James Tschanz,et al. Impact of Parameter Variations on Circuits and Microarchitecture , 2006, IEEE Micro.
[26] Martin Radetzki,et al. Fault Tolerant Network on Chip Switching With Graceful Performance Degradation , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[27] Tao Li,et al. Architecting reliable multi-core network-on-chip for small scale processing technology , 2010, 2010 IEEE/IFIP International Conference on Dependable Systems & Networks (DSN).
[28] Juha Plosila,et al. Current Challenges in Embedded Communication Systems , 2010, Int. J. Embed. Real Time Commun. Syst..
[29] Armin Alaghi,et al. Online Network-on-Chip Switch Fault Detection and Diagnosis Using Functional Switch Faults , 2008, J. Univers. Comput. Sci..
[30] David Blaauw,et al. ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon , 2006, IEEE Design & Test of Computers.
[31] Chita R. Das,et al. ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).
[32] S. Borkar,et al. An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS , 2008, IEEE Journal of Solid-State Circuits.
[33] Meeta Sharma Gupta,et al. Understanding Voltage Variations in Chip Multiprocessors using a Distributed Power-Delivery Network , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.
[34] Alain Greiner,et al. Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures , 2007, First International Symposium on Networks-on-Chip (NOCS'07).
[35] Zhiyi Yu,et al. A 167-Processor Computational Platform in 65 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.
[36] Stephen W. Keckler,et al. Regional congestion awareness for load balance in networks-on-chip , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.
[37] Hannu Tenhunen,et al. System-level exploration of run-time clusterization for energy-efficient on-chip communication , 2009, 2009 2nd International Workshop on Network on Chip Architectures.
[38] Fabien Clermidy,et al. A Reconfigurable Baseband Platform Based on an Asynchronous Network-on-Chip , 2008, IEEE Journal of Solid-State Circuits.
[39] Robert C. Aitken,et al. Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS , 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.
[40] Arnab Banerjee,et al. An Energy and Performance Exploration of Network-on-Chip Architectures , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[41] Sriram R. Vangal,et al. A 5-GHz Mesh Interconnect for a Teraflops Processor , 2007, IEEE Micro.
[42] Mikyung Kang,et al. Design and Development of a Run-Time Monitor for Multi-Core Architectures in Cloud Computing , 2011, Sensors.
[43] David Wentzlaff,et al. Processor: A 64-Core SoC with Mesh Interconnect , 2010 .
[44] Jörg Henkel,et al. Dependability and Security Will Change Embedded Computing , 2008, Computer.
[45] Priyadarsan Patra,et al. Impact of Process and Temperature Variations on Network-on-Chip Design Exploration , 2008 .
[46] R. Mullins. Minimising Dynamic Power Consumption in On-Chip Networks , 2006, 2006 International Symposium on System-on-Chip.
[47] Meeta Sharma Gupta,et al. System level analysis of fast, per-core DVFS using on-chip switching regulators , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.
[48] Ethiopia Nigussie,et al. Process variation tolerant on-chip communication using receiver and driver reconfiguration , 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).
[49] J.A. Tierno,et al. A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI , 2008, IEEE Journal of Solid-State Circuits.
[50] Mahmut T. Kandemir,et al. Leakage Current: Moore's Law Meets Static Power , 2003, Computer.