Practical techniques for performance estimation of processors

Performance estimation of processor is important to select the right processor for an application. Poorly chosen processors can either under perform very badly or over perform but with high cost. Most previous work on performance estimation are based on generating the development tools, i.e., compilers, assemblers etc from a processor description file and then additionally generating an instruction set simulator to get the performance. In this work we present a simpler strategy for performance estimation. We propose an estimation technique based on the intermediate format of an application. The estimation process does not require the generation of all the development tools as in the prevalent methods. As a result our method is not only cheaper but also faster.

[1]  鈴木 敬,et al.  Efficient Software Performance Estimation Methods for Hardware/Software Codesign , 1996 .

[2]  Todd M. Austin,et al.  SimpleScalar: An Infrastructure for Computer System Modeling , 2002, Computer.

[3]  Rajat Moona,et al.  Processor modeling for hardware software codesign , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

[4]  Peter Puschner.  Is Worst-Case Execution-Time Analysis a Non-Problem? — Towards New Software and Hardware Architectures , 2002 .

[5]  Subhash Chandra,et al.  Retargetable functional simulator using high level processor models , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

[6]  Sharad Malik,et al.  Processor evaluation in an embedded systems design environment , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

[7]  Rajat Moona,et al.  Processor models for retargetable tools , 2000, Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype (Cat. No.PR00668).

[8]  Markus Freericks,et al.  Describing instruction set processors using nML , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[9]  Alberto L. Sangiovanni-Vincentelli,et al.  A compilation-based software estimation scheme for hardware/software co-simulation , 1999, Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450).

[10]  Reinhold Heckmann,et al.  Worst case execution time prediction by static program analysis , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

[11]  Srinivas Devadas,et al.  ISDL: an instruction set description language for retargetability , 1997, DAC.

[12]  Per Stenström,et al.  Timing anomalies in dynamically scheduled microprocessors , 1999, Proceedings 20th IEEE Real-Time Systems Symposium (Cat. No.99CB37054).

[13]  Amer Baghdadi,et al.  Combining a Performance Estimation Methodology with a Hardware/Software Codesign Flow Supporting Multiprocessor Systems , 2002, IEEE Trans. Software Eng..

[14]  Vikram S. Adve,et al.  LLVM: a compilation framework for lifelong program analysis & transformation , 2004, International Symposium on Code Generation and Optimization, 2004. CGO 2004..

[15]  Peter Pirsch,et al.  A platform-independent methodology for performance estimation of streaming media applications , 2002, Proceedings. IEEE International Conference on Multimedia and Expo.