Investigation on Variability in Metal-Gate Si Nanowire MOSFETs: Analysis of Variation Sources and Experimental Characterization

The characteristic variability in gate-all-around (GAA) Si nanowire (NW) metal-oxide-semiconductor field-effect transistors (SNWTs) is analyzed and experimentally investigated in this paper. First, the main variation sources in SNWTs are overviewed, with the detailed discussion on the specific sources of NW cross-sectional shape variation, random dopant fluctuation in NW source/drain extension regions and NW line-edge roughness (LER). Then, following the measurement-modeling approach, via calibrated statistical simulation that is based on the modified analytical model for GAA SNWTs with corrections of quantum effects and quasi-ballistic transport, the variability sources in SNWTs are experimentally extracted from the measured devices with 10-nm-diameter NW channels and TiN metal gate. The results indicate that NW radius variation and metal-gate work function variation dominate both the threshold voltage and on-current variations due to the ultrascaled dimensions and strong quantum effects of GAA NW structure. The NW LER also contributes, but relatively less, to the threshold voltage variation.

[1]  E. Suzuki,et al.  Characterization of metal-gate FinFET variability based on measurements and compact model analyses , 2008, 2008 IEEE International Electron Devices Meeting.

[2]  J. A. López-Villanueva,et al.  Effects of the inversion-layer centroid on the performance of double-gate MOSFETs , 2000 .

[3]  Ru Huang,et al.  New Self-Aligned Silicon Nanowire Transistors on Bulk Substrate Fabricated by Epi-Free Compatible CMOS Technology: Process Integration, Experimental Characterization of Carrier Transport and Low Frequency noise , 2007, 2007 IEEE International Electron Devices Meeting.

[4]  A. Asenov,et al.  Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness , 2003 .

[5]  Y. Nara,et al.  Impact of additional factors in threshold voltage variability of metal/high-k gate stacks and its reduction by controlling crystalline structure and grain size in the metal gates , 2008, 2008 IEEE International Electron Devices Meeting.

[6]  Yiming Li,et al.  Random-Dopant-Induced Variability in Nano-CMOS Devices and Digital Circuits , 2009, IEEE Transactions on Electron Devices.

[7]  A. Toriumi,et al.  Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET's , 1994 .

[8]  Andrew R. Brown,et al.  Simulation of statistical variability in nano-CMOS transistors using drift-diffusion, Monte Carlo and non-equilibrium Green’s function techniques , 2009 .

[9]  M.J.M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[10]  Takeuchi Kiyoshi,et al.  Random Fluctuations in Scaled MOS Devices , 2009 .

[11]  K. Banerjee,et al.  Modeling and analysis of grain-orientation effects in emerging metal-gate devices and implications for SRAM reliability , 2008, 2008 IEEE International Electron Devices Meeting.

[12]  A. Hikavyy,et al.  Gatestacks for scalable high-performance FinFETs , 2007, 2007 IEEE International Electron Devices Meeting.

[13]  E. Nowak,et al.  High-performance CMOS variability in the 65-nm regime and beyond. IBM J Res And Dev , 2006 .

[14]  G. Ghibaudo,et al.  New extraction method for gate bias dependent series resistance in nanometric double gate transistors , 2005, Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005..

[15]  D.S.H. Chan,et al.  Performance breakthrough in 8 nm gate length Gate-All-Around nanowire transistors using metallic nanowire contacts , 2008, 2008 Symposium on VLSI Technology.

[16]  T. Fukai,et al.  Understanding Random Threshold Voltage Fluctuation by Comparing Multiple Fabs and Technologies , 2007, 2007 IEEE International Electron Devices Meeting.

[17]  Ru Huang,et al.  Analog/RF Performance of Si Nanowire MOSFETs and the Impact of Process Variation , 2007, IEEE Transactions on Electron Devices.

[18]  Donggun Park,et al.  TSNWFET for SRAM cell application: Performance variation and process dependency , 2008, 2008 Symposium on VLSI Technology.

[19]  M. Shur,et al.  Low ballistic mobility in submicron HEMTs , 2002, IEEE Electron Device Letters.

[20]  Kelin Kuhn,et al.  Managing Process Variation in Intel’s 45nm CMOS Technology , 2008 .

[21]  H. Wong,et al.  Impact of a Process Variation on Nanowire and Nanotube Device Performance , 2007, IEEE Transactions on Electron Devices.

[22]  Xing Zhang,et al.  Experimental Investigations on Carrier Transport in Si Nanowire Transistors: Ballistic Efficiency and Apparent Mobility , 2008, IEEE Transactions on Electron Devices.

[23]  Y. Nishi,et al.  Physical model of the impact of metal grain work function variability on emerging dual metal gate MOSFETs and its implication for SRAM reliability , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[24]  R. Tsuchiya,et al.  Comprehensive study on vth variability in silicon on Thin BOX (SOTB) CMOS with small random-dopant fluctuation: Finding a way to further reduce variation , 2008, 2008 IEEE International Electron Devices Meeting.

[25]  B. Ryu,et al.  High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[26]  Thomas Ernst,et al.  Hydrogen annealing of arrays of planar and vertically stacked Si nanowires , 2007 .

[27]  B. Iñíguez,et al.  Continuous analytic I-V model for surrounding-gate MOSFETs , 2004, IEEE Electron Device Letters.

[28]  Yuan Taur,et al.  An analytic model for threshold voltage shift due to quantum confinement in surrounding gate MOSFETs with anisotropic effective mass , 2009 .

[29]  O. Faynot,et al.  Novel Si-based nanowire devices: Will they serve ultimate MOSFETs scaling or ultimate hybrid integration? , 2008, 2008 IEEE International Electron Devices Meeting.

[30]  Andrew R. Brown,et al.  Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs , 2003 .

[31]  Ru Huang,et al.  Investigation of Nanowire Line-Edge Roughness in Gate-All-Around Silicon Nanowire MOSFETs , 2010, IEEE Transactions on Electron Devices.

[32]  H. Onodera.  Variability modeling and impact on design , 2008, 2008 IEEE International Electron Devices Meeting.