400 Gbps energy-efficient multi-field packet classification on FPGA

Packet classification is a network kernel function that has been widely researched over the past decade. However, most previous work has only focused on achieving high-throughput without considering its energy-efficiency implications. With the rapid growth of Internet, energy-efficiency has become an important metric for networks. We present the design of an energy-efficient packet classifier on Field-Programmable Gate Arrays (FPGA). The classifier is arranged as a 2-dimensional array of processing elements to enable sustained high throughput. We developed a memory activation scheduling technique that is able to significantly reduce memory power dissipation by selectively activating memory blocks. We conducted experiments using real-life rule sets and packet traces to evaluate our design. The experimental results show that with the memory activation scheduling technique, our design achieves 1.8× greater energy-efficiency compared with a baseline implementation without this energy optimization. With 6 individual classifiers on a single chip and a rule set of size IK, our design sustains a throughput of 400 Gbps for minimum size (40 bytes) packets and can process over 100 Gbps network traffic per Joule. Compared with state-of-the-art solutions, we achieve over 1.7× improvement in energy-efficiency.