Average-case optimized technology mapping of one-hot domino circuits

This paper presents a technology mapping technique for optimizing the average-case delay of asynchronous combinational circuits implemented using domino logic and one-hot encoded outputs. The technique minimizes the critical path for common input patterns at the possible expense of making less common critical paths longer. To demonstrate the application of this technique, we present a case study of a combinational length decoding block, an integral component of an Asynchronous Instruction Length Decoder (AILD) which can be used in Pentium(R) processors. The experimental results demonstrate that the average-case delay of our mapped circuits can be dramatically lower than the worst-case delay of the circuits obtained using conventional worst-case mapping techniques.

[1]  Steven M. Nowick.  Design of a low-latency asynchronous adder using speculative completion , 1996 .

[2]  Neil Weste,et al.  Principles of CMOS VLSI Design , 1985 .

[3]  Jianwei Liu,et al.  Dynamic logic in four-phase micropipelines , 1996, Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[4]  T. E. Williarns,et al.  A Zero-overhead Self-timed 160ns 54b CMOS Divider , 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[5]  Mark Horowitz,et al.  A zero-overhead self-timed 160-ns 54-b CMOS divider , 1991 .

[6]  Steven M. Burns,et al.  General conditions for the decomposition of state holding elements , 1996, Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[7]  Peter A. Beerel,et al.  Optimizing average-case delay in technology mapping of burst-mode circuits , 1996, Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[8]  Peter A. Beerel,et al.  A Low-Control-Overhead Asynchronous Differential Equation Solver , 1996, ESSCIRC '96: Proceedings of the 22nd European Solid-State Circuits Conference.

[9]  David L. Dill,et al.  Exact two-level minimization of hazard-free logic with multiple-input changes , 1992, ICCAD.

[10]  Massoud Pedram,et al.  Computing the area versus delay trade-off curves in technology mapping , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Stephen H. Unger,et al.  Asynchronous sequential switching circuits , 1969 .

[12]  Alberto Sangiovanni-Vincentelli,et al.  Logic synthesis for vlsi design , 1989 .

[13]  Jim D. Garside,et al.  AMULET2e: an asynchronous embedded controller , 1997, Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[14]  Peter A. Beerel,et al.  The design and verification of a high-performance low-control-overhead asynchronous differential equation solver , 1997, Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[15]  Andrew Wolfe,et al.  A high-speed asynchronous decompression circuit for embedded processors , 1997, Proceedings Seventeenth Conference on Advanced Research in VLSI.

[16]  Robert K. Brayton,et al.  Performance-oriented technology mapping , 1990 .

[17]  Giovanni De Micheli,et al.  Automatic Technology Mapping for Generalized Fundamental-Mode Asynchronous Designs , 1993, 30th ACM/IEEE Design Automation Conference.

[18]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[19]  Steven M. Burns,et al.  The design of an asynchronous microprocessor , 1989, CARN.

[20]  Peter A. Beerel,et al.  A heuristic covering technique for optimizing average-case delay in the technology mapping of asynchronous burst-mode circuits , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.

[21]  P. Marston,et al.  Designing asynchronous standby circuits for a low-power pager , 1999 .

[22]  David L. Dill,et al.  Synthesis of Asynchronous Controllers for Heterogeneous Systems , 1994 .

[23]  Marly Roncken,et al.  Asynchronous circuits for low power: a DCC error corrector , 1994, IEEE Design & Test of Computers.

[24]  Kenneth Y. Yun.  Automatic synthesis of extended burst-mode circuits using generalized C-elements , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.

[25]  Peter A. Beerel,et al.  Speculative completion for the design of high-performance asynchronous dynamic adders , 1997, Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[26]  Steven M. Nowick,et al.  Asynchronous Circuit Design: Motivation, Background, & Methods , 1995 .

[27]  Paul I. Pénzes,et al.  The design of an asynchronous MIPS R3000 microprocessor , 1997, Proceedings Seventeenth Conference on Advanced Research in VLSI.

[28]  Ken Stevens,et al.  The Post Office experience: designing a large asynchronous chip , 1993, Integr..