Defect tolerant SRAM based FPGAs

We propose a new approach to redundancy for field programmable gate arrays (FPGAs) which uses a novel reconfiguration network. Modifications are made to the wiring segments and a spare element is incorporated at the end of each row. By using the technique it will be possible to construct arrays 10 times larger than are commercially economic at present. The scheme is applicable to any SRAM based FPGA and keeps full software compatability with existing design tools.<<ETX>>