Optimization of memory allocation for real-time video processing on FPGA

We present an optimization model for the allocation of shift registers to dual ported FPGA memory blocks. Shift registers are used in real-time video processing for the storage of data flow dependencies. The model is formalized into a mixed integer linear program that can be executed using a general solver. Allocation results from realistic video systems verify the correctness of the model. This model serves as a formal specification and setup for the development of an efficient allocation heuristic.

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