On the Generation of Compact Deterministic Test Sets for BIST Ready Designs

In this work we consider ATPG methods tailored to BIST ready designs to improve compression of external tests for such designs. Proposed ATPG reduces external test set sizes and test data volumes by 24% in comparison to that obtained by a state of the art commercial ATPG for BIST ready designs.

[1]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .

[2]  Bernard Courtois,et al.  Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers , 1995, IEEE Trans. Computers.

[3]  Nur A. Touba,et al.  Survey of Test Vector Compression Techniques , 2006, IEEE Design & Test of Computers.

[4]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[5]  Peter Wohl,et al.  Fully X-tolerant, very high scan compression , 2010, Design Automation Conference.

[6]  P. A. Krauss,et al.  Efficient fault ordering for automatic test pattern generation for sequential circuits , 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).

[7]  Mario H. Konijnenburg,et al.  Compact test sets for industrial circuits , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[8]  B. Koneman,et al.  LFSR-Coded Test Patterns for Scan Designs , 1993 .

[9]  Ad J. van de Goor,et al.  Test point insertion that facilitates ATPG in reducing test time and data volume , 2002, Proceedings. International Test Conference.

[10]  Janusz Rajski,et al.  Logic BIST for large industrial designs: real issues and case studies , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[11]  P. Goel Test Generation and Dynamic Compaction of Tests , 1979 .

[12]  Chen Wang,et al.  On the generation of compact test sets , 2013, 2013 IEEE International Test Conference (ITC).

[13]  Nilanjan Mukherjee,et al.  Embedded deterministic test for low cost manufacturing test , 2002, Proceedings. International Test Conference.

[14]  Irith Pomeranz,et al.  The accidental detection index as a fault ordering heuristic for full-scan circuits , 2005, Design, Automation and Test in Europe.

[15]  S. Hellebrand,et al.  Pattern generation for a deterministic BIST scheme , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[16]  Rolf Drechsler,et al.  Using a two-dimensional fault list for compact Automatic Test Pattern Generation , 2009, 2009 10th Latin American Test Workshop.

[17]  Motoyuki Sato,et al.  DART: Dependable VLSI test architecture and its implementation , 2012, 2012 IEEE International Test Conference.

[18]  Irith Pomeranz,et al.  COMPACTEST: a method to generate compact test sets for combinational circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  L. H. Goldstein,et al.  SCOAP: Sandia Controllability/Observability Analysis Program , 1988, 17th Design Automation Conference.

[20]  J. Paul Roth,et al.  Diagnosis of automata failures: a calculus and a method , 1966 .