Design of very high throughput with low complexity output MIMO decoder

A low-complexity soft-output decoding algorithm is proposed for MIMO detection. A VLSI architecture is further proposed to support high-throughput MIMO decoding. The simulation and implementation results show that the proposed algorithm and VLSI architecture can approach the performance of the conventional soft-output MIMO decoding algorithms with lower complexity and higher decoding throughput. The proposed algorithm and VLSI architecture would be promising for emerging MIMO applications such as HSDPA, 802.11n, 802.16e and 802.20. It also shows potentials for the MAGNET date rate classes.