Performance analysis of a separate address/data bus multiprocessor system

Abstract This paper presents a performance model of a special shared bus multiprocessor system, that features: (1) separate address‐bus and data‐bus with split transaction, pipelined cycle; (2) two‐level cache structure; and (3) multiple main memory and I/O modules. Accessing conflicts in these subsystems, maintaining shared data and DMA transfer between memory and I/O subsystems are also considered in the model. The representation for the complex behavior of a whole multiprocessor system distinguishes the model from others that present only one major subsystem. The performance model can be used not only to assist in evaluating the architectural design of aparticular system, but also directly utilized to identify subsystem bottlenecks and their causes in order to make performance improvements. Results show that: (1) the values of some key design parameters, such as cache line size and data‐bus width that yield the best throughput, are dependent on the performance of subsystems; (2) choosing the data‐bus w...