SoC-FPGA implementation of the sparse fast fourier transform algorithm

This brief presents the SoC-FPGA implementation of the modified Nearly Optimal Sparse Fast Fourier Transform (sFFT) algorithm. The implementation was carried out by using hardware/software co-design based on software profiling that helped to find out that pseudo-random Spectral Permutation, Windowing, and Sub-Sampling (SPWS) are the signal processing operations that require most processing time in the modified sFFT algorithm. Then, by considering the software profiling results, a SPWS hardware accelerator was designed by using structural and generic VHDL. The SPWS hardware accelerator is composed of one Random Sampling Direct Memory Access Controller (RS-DMAC) and one Windowing and Sampling (WS) circuit. Later, the SPWS is integrated into the FPGA fabric of the SoC-FPGA to accelerate the whole modified sFFT algorithm. In this case, the software sub-system is managed by the Real Time Operating System (RTOS) QNX Neutrino. Finally, the verification results showed that 4.6 times acceleration is achieved for the SPWS, and 3.1 times acceleration is achieved for the whole modified sFFT algorithm when it is compared with the fully software implementation.