Recent Technology Advances of Emerging Memories

Editor’s note: Phase change memory, spin-transfer torque random access memory, and resistive random access memory are three major emerging memory technologies that receive tremendous attentions from both academia and industry. In this survey article, the authors summarize the latest research progress of these technologies in device engineering, circuit design, computer architecture, and application. —Tei-Wei Kuo, National Taiwan University

[1]  M. Hosomi,et al.  A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[2]  Yuan Xie,et al.  Access scheme of Multi-Level Cell Spin-Transfer Torque Random Access Memory and its optimization , 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

[3]  Yiran Chen,et al.  Nonvolatile Memory Design: Magnetic, Resistive, and Phase Change , 2011 .

[4]  Cong Xu,et al.  NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Yu Wang,et al.  Memristor-based approximated computation , 2013, International Symposium on Low Power Electronics and Design (ISLPED).

[6]  Yiran Chen,et al.  A new field-assisted access scheme of STT-RAM with self-reference capability , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[7]  Kiyoung Choi,et al.  DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture , 2014, 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA).

[8]  Yiran Chen,et al.  Reduction and IR-drop compensations techniques for reliable neuromorphic computing systems , 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[9]  Yu Wang,et al.  Training itself: Mixed-signal training acceleration for memristor-based neural network , 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

[10]  H. Ohno,et al.  Perpendicular-anisotropy CoFeB-MgO based magnetic tunnel junctions scaling down to 1X nm , 2014, 2014 IEEE International Electron Devices Meeting.

[11]  Mohammad Arjomand,et al.  Reducing access latency of MLC PCMs through line striping , 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).

[12]  H. Wong,et al.  A 1TnR array architecture using a one-dimensional selection device , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[13]  Tetsuo Endoh,et al.  10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[14]  S. O. Park,et al.  Challenging issues for terra-bit-level perpendicular STT-MRAM , 2014, 2014 IEEE International Electron Devices Meeting.

[15]  Jian Wu,et al.  Technology and circuit optimization of resistive RAM for low-power, reproducible operation , 2014, 2014 IEEE International Electron Devices Meeting.

[16]  Karl Hofmann,et al.  Comprehensive statistical investigation of STT-MRAM thermal stability , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[17]  Yiran Chen,et al.  Prefetching techniques for STT-RAM based last-level cache in CMP systems , 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

[18]  Yiran Chen,et al.  Memristor Crossbar-Based Neuromorphic Computing System: A Case Study , 2014, IEEE Transactions on Neural Networks and Learning Systems.

[19]  Y. J. Chen,et al.  Utilizing Sub-5 nm sidewall electrode technology for atomic-scale resistive memory fabrication , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[20]  Yiran Chen,et al.  State-restrict MLC STT-RAM designs for high-reliable high-performance memory system , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[21]  Tony F. Wu,et al.  Monolithic 3D integration of logic and memory: Carbon nanotube FETs, resistive RAM, and silicon FETs , 2014, 2014 IEEE International Electron Devices Meeting.

[22]  Kumiko Nomura,et al.  Novel nonvolatile memory hierarchies to realize "normally-off mobile processors" , 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

[23]  L. Goux,et al.  Lateral and vertical scaling impact on statistical performances and reliability of 10nm TiN/Hf(Al)O/Hf/TiN RRAM devices , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[24]  G. Kar,et al.  Co/Ni based p-MTJ stack for sub-20nm high density stand alone and high performance embedded memory application , 2014, 2014 IEEE International Electron Devices Meeting.

[25]  Y. Chih,et al.  1Kbit FinFET Dielectric (FIND) RRAM in pure 16nm FinFET CMOS logic process , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[26]  A. Cabrini,et al.  Intrinsic program instability in HfO2 RRAM and consequences on program algorithms , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[27]  Yiran Chen,et al.  Vortex: Variation-aware training for memristor X-bar , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[28]  Seung H. Kang,et al.  Systematic optimization of 1 Gbit perpendicular magnetic tunnel junction arrays for 28 nm embedded STT-MRAM and beyond , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[29]  W. C. Chien,et al.  Greater than 2-bits/cell MLC storage for ultra high density phase change memory using a novel sensing scheme , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

[30]  D. Apalkov,et al.  Physics-based compact modeling framework for state-of-the-art and emerging STT-MRAM technology , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[31]  Rami G. Melhem,et al.  CAFO: Cost aware flip optimization for asymmetric memories , 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).

[32]  Hao Jiang,et al.  RENO: A high-efficient reconfigurable neuromorphic computing accelerator design , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[33]  Hao Jiang,et al.  A spiking neuromorphic design with resistive crossbar , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[34]  Daisuke Suzuki,et al.  Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

[35]  Yiran Chen,et al.  An efficient STT-RAM-based register file in GPU architectures , 2015, The 20th Asia and South Pacific Design Automation Conference.

[36]  Yu Wang,et al.  MErging the Interface: Power, area and accuracy co-optimization for RRAM crossbar-based mixed-signal computing system , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[37]  Hagop Nazarian,et al.  Self-limited RRAM with ON/OFF resistance ratio amplification , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

[38]  R. Jordan,et al.  NVM neuromorphic core with 64k-cell (256-by-256) phase change memory synaptic array with on-chip neuron circuits for continuous in-situ learning , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[39]  Satoshi Takaya,et al.  7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[40]  Chankyung Kim,et al.  7.4 A covalent-bonded cross-coupled current-mode sense amplifier for STT-MRAM with 1T1MTJ common source-line structure array , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[41]  T. Endoh,et al.  Novel oxygen showering process (OSP) for extreme damage suppression of sub-20nm high density p-MTJ array without IBE treatment , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

[42]  J. Nowak,et al.  STT-MRAM with double magnetic tunnel junctions , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[43]  Qi Liu,et al.  Demonstration of 3D vertical RRAM with ultra low-leakage, high-selectivity and self-compliance memory cells , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[44]  Yiran Chen,et al.  An EDA framework for large scale hybrid neuromorphic computing systems , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[45]  Ning Ge,et al.  A holistic tri-region MLC STT-RAM design with combined performance, energy, and reliability optimizations , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[46]  Zhiwei Li,et al.  Binary neural network with 16 Mb RRAM macro chip for classification and online training , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[47]  Kartik Mohanram,et al.  SECRET: Smartly EnCRypted Energy efficienT non-volatile memories , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[48]  S. Burc Eryilmaz,et al.  Four-layer 3D vertical RRAM integrated with FinFET as a versatile computing unit for brain-inspired cognitive information processing , 2016, 2016 IEEE Symposium on VLSI Technology.

[49]  E. S. Jung,et al.  Highly functional and reliable 8Mb STT-MRAM embedded in 28nm logic , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[50]  G. Cibrario,et al.  Fundamental variability limits of filament-based RRAM , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[51]  H. L. Lung,et al.  ALD-based confined PCM with a metallic liner toward unlimited endurance , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[52]  Catherine Graves,et al.  Dot-product engine for neuromorphic computing: Programming 1T1M crossbar to accelerate matrix-vector multiplication , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[53]  Tom Zhong,et al.  Reliability study of perpendicular STT-MRAM as emerging embedded memory qualified for reflow soldering at 260°C , 2016, 2016 IEEE Symposium on VLSI Technology.

[54]  Yiran Chen,et al.  Design and Implementation of a 4Kb STT-MRAM with Innovative 200nm Nano-ring Shaped MTJ , 2016, ISLPED.

[55]  C. Lam,et al.  Reliability study of a 128Mb phase change memory chip implemented with doped Ga-Sb-Ge with extraordinary thermal stability , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[56]  Steve S. Chung,et al.  Fully CMOS compatible 3D vertical RRAM with self-aligned self-selective cell enabling sub-5nm scaling , 2016, 2016 IEEE Symposium on VLSI Technology.

[57]  Yoshishige Suzuki,et al.  Novel voltage controlled MRAM (VCM) with fast read/write circuits for ultra large last level cache , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[58]  Amirali Ghofrani,et al.  A low-power hybrid reconfigurable architecture for resistive random-access memories , 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).

[59]  Miao Hu,et al.  ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars , 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).

[60]  Tom Zhong,et al.  Achieving Sub-ns switching of STT-MRAM for future embedded LLC applications through improvement of nucleation and propagation switching mechanisms , 2016, 2016 IEEE Symposium on VLSI Technology.

[61]  H. Kanaya,et al.  4Gbit density STT-MRAM using perpendicular MTJ realized with compact cell structure , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[62]  Jun Wang,et al.  AOS: Adaptive overwrite scheme for energy-efficient MLC STT-RAM cache , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[63]  Mohammad Arjomand,et al.  Boosting Access Parallelism to PCM-Based Main Memory , 2016, ISCA.

[64]  T. Magis,et al.  Data retention extraction methodology for perpendicular STT-MRAM , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[65]  Mary Jane Irwin,et al.  LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches , 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).

[66]  Hiroshi Nakamura,et al.  7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[67]  Cong Xu,et al.  NVSim-VXs: An improved NVSim for variation aware STT-RAM simulation , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[68]  F. Xiong,et al.  Towards ultimate scaling limits of phase-change memory , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[69]  Yiran Chen,et al.  Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[70]  Chenchen Liu,et al.  Rescuing memristor-based neuromorphic design with high defects , 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

[71]  Yiran Chen,et al.  PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning , 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).

[72]  Saida Daisuke,et al.  Sub-3 ns pulse with sub-100 uA switching of 1x-2x nm perpendicular MTJ for high-performance embedded STT-MRAM towards sub-20 nm CMOS , 2017 .

[73]  Yiran Chen,et al.  Extending the lifetime of object-based NAND flash device with STT-RAM/DRAM hybrid buffer , 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

[74]  Gang Quan,et al.  A statistical STT-RAM retention model for fast memory subsystem designs , 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).