Effect of thermal annealing on TSV Cu protrusion and local stress

Through silicon vias (TSVs) are regarded as one of the key enabling component to achieve three-dimensional (3D) integrated circuit (IC) functionality. In this paper, we present the investigation on TSV protrusion and stress at different annealing conditions tested by means of optical profiler and high efficiency micro-Raman microscopy. Finite element method is utilized to model and simulate the thermo-mechanical behavior of the TSV having a diameter of 20 μm and a depth of 120 μm under different annealing temperatures. The measured protrusion increases with annealing temperature below 400°C, and then decreases when being further annealed. The maximum measured silicon stress as a function of annealing temperature has shown similar trend to the protrusion. The pre-annealing has limited effect on protrusion, but is helpful to reduce the silicon stress.

[1]  K. Teo,et al.  Stress evolution in surrounding silicon of Cu-filled through-silicon via undergoing thermal annealing by multiwavelength micro-Raman spectroscopy , 2011 .

[2]  Ehrenfried Zschech,et al.  NanoXCT—A High‐Resolution Technique For TSV Characterization , 2011 .

[3]  Tobias Neubrand,et al.  Non-destructive inspection of through mould vias in stacked embedded packages by micro-CT , 2011, 2011 IEEE 13th Electronics Packaging Technology Conference.

[4]  Suk-kyu Ryu,et al.  Micro-Raman spectroscopy and analysis of near-surface stresses in silicon around through-silicon vias for three-dimensional interconnects , 2012 .

[5]  Tobias Neubrand,et al.  Improved inspection of miniaturised interconnections by digital X-ray inspection and computed tomography , 2010, 2010 12th Electronics Packaging Technology Conference.

[6]  Christian Weinekoetter.  X‐Ray Nanofocus CT: Visualising Of Internal 3D‐Structures With Submicrometer Resolution , 2008 .

[7]  Peter Ramm,et al.  Handbook of 3D integration : technology and applications of 3D integrated circuits , 2012 .

[8]  E. Zschech,et al.  Sub‐imaging Techniques For 3D‐Interconnects On Bonded Wafer Pairs , 2010 .

[9]  Yasumitsu Orii,et al.  TSV diagnostics by X-ray microscopy , 2011, 2011 IEEE 13th Electronics Packaging Technology Conference.

[10]  S. Rehbein,et al.  Dynamical X‐ray Microscopy Study of Stress‐Induced Voiding in Cu Interconnects , 2009 .

[11]  Alain C. Diebold,et al.  Applying x-ray microscopy and finite element modeling to identify the mechanism of stress-assisted void growth in through-silicon vias , 2011 .

[12]  Li Hong Yu,et al.  Non-destructive testing of a high dense small dimension through silicon via (TSV) array structures by using 3D X-ray computed tomography method (CT scan) , 2010, 2010 12th Electronics Packaging Technology Conference.