Impact of spacer interface charges on performance and reliability of low temperature transistors for 3D sequential integration

The impact of interface charges under the gate spacer on FDSOI devices integrated in low temperature process are explored. A great number of traps (~1013/cm2) are identified on the interface between the spacer oxide and the silicon film using Terman's method for interface states characterization. Thanks to electrical characterization and TCAD simulations, it is shown that the trapped charges induce the formation of a depleted region in the vicinities of the spacer. Moreover, a strong degradation of performances on underlap channels is observed. The spacer charges influence on reliability measurements is finally explored.

[1]  X. Garros,et al.  Performance and Reliability of a Fully Integrated 3D Sequential Technology , 2018, 2018 IEEE Symposium on VLSI Technology.

[2]  X. Garros,et al.  PBTI mechanisms in La containing Hf-based oxides assessed by very Fast IV measurements , 2010, 2010 International Electron Devices Meeting.

[3]  O. Faynot,et al.  First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers , 2016, 2016 IEEE Symposium on VLSI Technology.

[4]  Dimitri Linten,et al.  Accelerated Capture and Emission (ACE) Measurement Pattern for Efficient BTI Characterization and Modeling , 2019, 2019 IEEE International Reliability Physics Symposium (IRPS).

[5]  A. Vandooren,et al.  BTI Reliability Improvement Strategies in Low Thermal Budget Gate Stacks for 3D Sequential Integration , 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

[6]  K.J.S. Cave,et al.  MOS (Metal Oxide Semiconductor) Physics and Technology , 1983 .

[7]  F. Clermidy,et al.  3D sequential integration opportunities and technology optimization , 2014, IEEE International Interconnect Technology Conference.