A Comparison of TMR With Alternative Fault-Tolerant Design Techniques for FPGAs

With growing interest in the use of SRAM-based FPGAs in space and other radiation environments, there is a greater need for efficient and effective fault-tolerant design techniques specific to FPGAs. Triple-modular redundancy (TMR) is a common fault mitigation technique for FPGAs and has been successfully demonstrated by several organizations. This technique, however, requires significant hardware resources. This paper evaluates three additional mitigation techniques and compares them to TMR. These include quadded logic, state machine encoding, and temporal redundancy, all well-known techniques in custom circuit technologies. Each of these techniques are compared to TMR in both area cost and fault tolerance. The results from this paper suggest that none of these techniques provides greater reliability and often require more resources than TMR.

[1]  Nand Kumar,et al.  Automated FSM Error Correction for Single Event Upsets , 2004 .

[2]  Earl E. Swartzlander,et al.  Quadruple time redundancy adders [error correcting adder] , 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

[3]  E. E. Swartzlander,et al.  Time redundant error correcting adders and multipliers , 1992, Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

[4]  M. Wirthlin,et al.  Improving FPGA Design Robustness with Partial TMR , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

[5]  C. Carmichael,et al.  A fault injection analysis of Virtex FPGA TMR design methodology , 2001, RADECS 2001. 2001 6th European Conference on Radiation and Its Effects on Components and Systems (Cat. No.01TH8605).

[6]  M. Caffrey,et al.  Evaluating TMR Techniques in the Presence of Single Event Upsets , 2003 .

[7]  M. Wirthlin,et al.  SEU-induced persistent error propagation in FPGAs , 2005, IEEE Transactions on Nuclear Science.

[8]  Carl Carmichael,et al.  Triple Module Redundancy Design Techniques for Virtex FPGAs, Application Note 197 , 2001 .

[9]  Régis Leveugle,et al.  Analysis and comparison of fault tolerant FSM architecture based on SEC codes , 1993, Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

[10]  Paul Graham,et al.  Accelerator validation of an FPGA SEU simulator , 2003 .

[11]  Earl E. Swartzlander,et al.  Quadruple Time Redundancy Adders , 2003 .

[12]  J. Wells.  AUTOMATIC RADIATION HARDENING OF FPGA DESIGNS USING SYNTHESIS TOOLS , 1998 .

[13]  M. Caffrey,et al.  Correcting single-event upsets through virtex partial configuration , 2000 .

[14]  D. B. Armstrong.  A general method of applying error correction to synchronous digital systems , 1961 .

[15]  J. Neumann.  Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components , 1956 .

[16]  Luigi Carro,et al.  Designing fault-tolerant techniques for SRAM-based FPGAs , 2004, IEEE Design & Test of Computers.

[17]  Michael J. Wirthlin,et al.  Hardness by design technique for field programmable gate arrays. , 2003 .

[18]  Mohamad R. Neilforoshan.  Fault tolerant computing in computer design , 2003 .

[19]  S. Niranjan,et al.  A comparison of fault-tolerant state machine architectures for space-borne electronics , 1996, IEEE Trans. Reliab..