An alternative algorithm is drawn in to fit the electrical characteristic curves, including Drain current versus Drain voltage and Drain current versus Gate voltage, on NFinFET devices. Devices are fabricated on SOI (silicon on insulator) wafers to prevent uncontrollable Ioff‘S, which are associated with Drain Induced Barrier Lowering (DIBL) and Punch-through effects. All-inclusive dominating variables, such as Drain, Source, and Gate, are certainly taken into account. In this study, this algorithm starts with fitting ID- VG characteristic curves, instead of ID- VD characteristic curves, to first more correctly search for threshold voltage (Vth,), followed by pinching down kN, and λ that are shown in the conventional current-voltage formula plus a current leakage term, which visibly contributes and thus matters as the applied gate bias to the substrate is comparably large. A conclusive procedure to make the model more feasible is then proposed to simplify the all-aspect electrical performances on the devices, in which the equivalent circuit is naively and deliberately ignored for the sake of avoiding the complicate circuitry and the issue of time-consuming convergence problem.