A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm2 cell in 32nm high-k metal-gate CMOS

This paper presents a configurable SRAM for low-voltage operation with constant-negative-level write buffer (CNL-WB) and level programmable wordline driver for single supply (LPWD-SS) operation. CNL-WB is suitable for compilable SRAMs and it improves write margin by featuring an automatic BL-level adjustment for configuration range of four to 512 cells/BL using a replica-BL technique. LPWD-SS optimizes the tradeoff between disturb and write margin of a memory cell, allowing a 60% shorter WL rise time than that of the conventional design [1] at 0.7V. A test-chip is fabricated in a 32nm high-k metal-gate CMOS technology with a 0.149µm2 6T-SRAM cell. Measurement results demonstrate a cell-failure rate improvement of two orders of magnitude for an array-configuration range of 64 to 256 rows by 64 to 256 columns.

[1]  Ying Zhang,et al.  A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[2]  Atsushi Kawasumi,et al.  A process-variation-tolerant dual-power-supply SRAM with 0.179µm2 Cell in 40nm CMOS using level-programmable wordline driver , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[3]  R. Wong,et al.  Scaling of 32nm low power SRAM with high-K metal gate , 2008, 2008 IEEE International Electron Devices Meeting.

[4]  T. Iwasaki,et al.  A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment , 2008, 2008 IEEE Symposium on VLSI Circuits.