Implementation of arithmetic primitives using truly deep submicron technology (TDST)

The invention of the transistor in 194 7 at Bell Laboratories revolutionised the electronics industry and created a powerful platform for emergence of new industries. The quest to increase the number of devices per chip over the last four decades has resulted in rapid transition from Small-Scale-Integration (SSI) and Large-Scale-Integration (LSI), through to the Very-Large-Scale-Integration (VLSI) technologies, incorporating approximately 10 to 100 million devices per chip. The next phase in this evolution is the Ultra-Large-Scale­ Integration (ULSI) aiming to realise new application domains currently not accessible to CMOS technology. Although technology is continuously evolving to produce smaller systems with minimised power dissipation, the IC industry is facing major challenges due to constraints on power density (W/cm2) and high dynamic (operating) and static (standby) power dissipation. Mobile multimedia communication and optical based technologies have rapidly become a significant area of research and development challenging a variety of technological fronts. The future emergence of 4G (4 Generation) wireless communications networks is further driving this development, requiring increasing levels of media rich content. The processing requirements for capture, conversion, compression, decompression, enhancement and display of higher quality multimedia, place heavy demands on current ULSI systems. This is also apparent for mobile applications and intelligent optical networks where silicon chip area and power dissipation become primary considerations. In addition to the requirements for very low power, compact size and real-time processing, the rapidly evolving nature of telecommunication networks means that flexible soft programmable systems capable of adaptation to support a number of different standards and/or roles become highly desirable. In order to fully realise the capabilities promised by the 4G and supporting intelligent networks, new enabling technologies are needed to facilitate the next generation of personal communications devices. Most of the current solutions to meet these challenges are based on various implementations of conventional architectures. For decades, silicon has been the main platform of computing, however it is slow, bulky, runs too hot, and is too expensive. Thus, new approaches to architectures, driving multimedia and future telecommunications systems, are needed in order to extend the life cycle of silicon technology. The emergence of Truly Deep Submicron Technology {TDST) and related 3-D interconnection technologies have provided potential alternatives from conventional architectures to 3-D system solutions, through integration of TDST, Vertical Software Mapping and Intelligent Interconnect Technology {IIT). The concept of Soft-Chip Technology (SCT) entails integration of "Soft-Processing Circuits" with "Soft-Configurable Circuits". This concept can effectively manipulate hardware primitives through vertical integration of control and data. Thus the notion of 3-D Soft-Chip emerges as a new design

[1]  Neil Weste,et al.  Principles of CMOS VLSI Design , 1985 .

[2]  Amine Bermak,et al.  High-density 16/8/4-bit configurable multiplier , 1997 .

[3]  Suhwan Kim,et al.  Low power parallel multiplier design for DSP applications through coefficient optimization , 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).

[4]  B. Alhalabi,et al.  Five new high-performance multiplexer-based 1-bit full adder cells , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

[5]  Kamran Eshraghian,et al.  Image capture using integrated 3D SoftChip technology , 2002, 5th IEEE International Conference on High Speed Networks and Multimedia Communication (Cat. No.02EX612).

[6]  Sung-Mo Kang,et al.  Modular charge recycling pass transistor logic (MCRPL) , 2000 .

[7]  Kamran Eshraghian,et al.  Design Methodology for a 3D SoftChip Video Processing Architecture , 2002 .

[8]  Sung-Mo Kang,et al.  A low-power 2.1 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

[9]  Kamran Eshraghian,et al.  Australian national networked tele-test facility for integrated systems , 2001, SPIE Micro + Nano Materials, Devices, and Applications.

[10]  Kamran Eshraghian,et al.  Phase-Only Hologram design of the Free Space Optical Crossbar Switch System , 2003 .

[11]  Kamran Eshraghian,et al.  A novel design of beam steering n-phase OPTO-ULSI processor for IIPS , 2004, Proceedings. DELTA 2004. Second IEEE International Workshop on Electronic Design, Test and Applications.

[12]  Kamran Eshraghian,et al.  Massively Parallel Intelligent Pixel Implementation of a Zerotree Entropy Video Codec for Multimedia Communications , 1999, VLSI.

[13]  Victor O. K. Li,et al.  Personal communication systems (PCS) , 1995, Proc. IEEE.

[14]  장훈,et al.  [서평]「Computer Organization and Design, The Hardware/Software Interface」 , 1997 .

[15]  Wu-Shiung Feng,et al.  New efficient designs for XOR and XNOR functions on the transistor level , 1994, IEEE J. Solid State Circuits.

[16]  Wolfgang Fichtner,et al.  Low-power logic styles: CMOS versus pass-transistor logic , 1997, IEEE J. Solid State Circuits.

[17]  Kamal Alameh,et al.  Applications of liquid crystal spatial light modulators in optical communications , 2002, 5th IEEE International Conference on High Speed Networks and Multimedia Communication (Cat. No.02EX612).

[18]  Kai Hwang,et al.  Computer arithmetic: Principles, architecture, and design , 1979 .

[19]  Yuke Wang,et al.  New 4-transistor XOR and XNOR designs , 2000, Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434).

[20]  A. Avizeinis,et al.  Signed Digit Number Representations for Fast Parallel Arithmetic , 1961 .

[21]  Massoud Pedram,et al.  Low power design methodologies , 1996 .

[22]  Kaustav Banerjee,et al.  3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration , 2001, Proc. IEEE.

[23]  G. M. Blair Designing low-power digital CMOS , 1994 .

[24]  Sung-Mo Kang,et al.  CMOS Pass-gate No-race Charge-recycling Logic (CPNCL) , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[25]  Andrew D. Booth,et al.  A SIGNED BINARY MULTIPLICATION TECHNIQUE , 1951 .

[26]  Michael John Sebastian Smith,et al.  Application-specific integrated circuits , 1997 .

[27]  Israel Koren Computer arithmetic algorithms , 1993 .

[28]  Magdy A. Bayoumi,et al.  A low power 10-transistor full adder cell for embedded architectures , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[29]  E Suhir,et al.  The Future of Microelectronics and Photonics , and the Role of Mechanical , Materials and Reliability Engineering , 2001 .

[30]  G. M. Blair The equivalence of twos-complement addition and the conversion of redundant-binary to twos-complement numbers , 1998 .

[31]  B. Robertson,et al.  Beam steering optical switches using LCOS: The 'ROSES' demonstrator , 2000, 2000 Digest of the LEOS Summer Topical Meetings. Electronic-Enhanced Optics. Optical Sensing in Semiconductor Manufacturing. Electro-Optics in Space. Broadband Optical Networks (Cat. No.00TH8497).

[32]  M P Dames,et al.  Efficient optical elements to generate intensity weighted spot arrays: design and fabrication. , 1991, Applied optics.

[33]  Haomin Wu,et al.  A new design of the CMOS full adder , 1992 .

[34]  Kamran Eshraghian,et al.  Adaptive Beam Control for Intelligent Reconfigurable Holographic Optical Switch , 2003 .

[35]  Uming Ko,et al.  Low-power design techniques for high-performance CMOS adders , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[36]  Sung-Mo Kang,et al.  No-race charge-recycling differential logic (NCDL) , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

[37]  B. Alhalabi,et al.  A novel low power multiplexer-based full adder cell , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

[38]  Sung-Mo Kang,et al.  Improved domino structures effective for high performance design , 1999 .

[39]  Kamran Eshraghian,et al.  Ultra High Bandwidth Image and Data Processing using 3-D Vertically Integrated Architectures , 2003 .

[40]  Wolfgang Nebel,et al.  Low power design in deep submicron electronics , 1997 .

[41]  Keshab K. Parhi,et al.  A fast VLSI adder architecture , 1992 .

[42]  J. E. Brewer,et al.  Extending the road beyond CMOS , 2002 .

[43]  Kamran Eshraghian,et al.  The Networked Tele-test Facility for Integrated Systems in Australia , 2002 .

[44]  D. G. Vass,et al.  Evolutionary development of advanced liquid crystal spatial light modulators. , 1989, Applied optics.

[45]  Noah Treuhaft,et al.  Scalable Processors in the Billion-Transistor Era: IRAM , 1997, Computer.

[46]  Kaustav Banerjee,et al.  Interconnect limits on gigascale integration (GSI) in the 21st century , 2001, Proc. IEEE.

[47]  D. Radhakrishnan,et al.  Low-voltage low-power CMOS full adder , 2001 .

[48]  Yingtao Jiang,et al.  Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates , 2002 .

[49]  Said F. Al-Sarawi,et al.  A Review of 3-D Packaging Technology , 1998 .

[50]  J. Bormans,et al.  3D computational graceful degradation , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[51]  Yuke Wang,et al.  Design and analysis of 10-transistor full adders using novel XOR-XNOR gates , 2000, WCC 2000 - ICSP 2000. 2000 5th International Conference on Signal Processing Proceedings. 16th World Computer Congress 2000.

[52]  H. Nakatsuka The new frontier created by high-bandwidth digital video systems and services , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[53]  J. Allebach,et al.  Synthesis of digital holograms by direct binary search. , 1987, Applied optics.