Improved compact thermal model for studying 3-D interconnect structures with low-k dielectrics

Compact thermal modeling is gaining significance as interconnect feature sizes continue to shrink, requiring increased computation times for full-field multi-scale simulations. Improved and expanded uses of an existing compact thermal modeling approach found in Gurrum et al. [A compact approach to on-chip interconnect heat conduction modeling using the finite element method, ASME J. Electron. Packaging (2007), accepted], Gurrum et al. [A novel compact method for thermal modeling of on-chip interconnects based on the finite element method, ASME, EEP 3, Electron. Photon. Packing Electr. Syst. Photon. Des. Nanotechnol. (2003) 441-445] are presented here. The first improvement rectifies a singularity that occurs in the previous compact model. This change allows for greater flexibility in mesh application, and a greater number of structures that can be analyzed. This work focuses on the application of the compact thermal model to two interconnect structures. The first geometry [S. Im, N. Srivastava, K. Banerjee, K. Goodson, Scaling analysis of multilevel interconnect temperatures for high performance ICS, IEEE Trans. Electron. Dev. 52 (12) (2005) 2710-2719] is a typical interconnect structure based on the ITRS 65nm technology node. A new transient compact model was applied to another geometry [J. Zhang, M. Bloomfield, J. Lu, R. Gutmann, T. Cale, Thermal stresses in 3D IC inter-wafer interconnects, Microelectron. Eng. 82 (3-4) (2005) 534-547], which is a more advanced technology with a through-the-die via structure. The second improvement of the compact model is extending the steady state finite element based model into a transient version. Full-field simulations have very large storage and memory requirements for transient analysis of complex structures. The advantage of this compact model is that in addition to increased efficiency, the methodology and implementation is similar to a traditional finite element analysis (FEA).

[1]  K. Banerjee,et al.  Scaling analysis of multilevel interconnect temperatures for high-performance ICs , 2005, IEEE Transactions on Electron Devices.

[2]  L. Codecasa,et al.  A novel approach for generating boundary condition independent compact dynamic thermal networks of packages , 2005, IEEE Transactions on Components and Packaging Technologies.

[3]  P. Maffezzoni,et al.  Compact thermal networks for modeling packages , 2004, IEEE Transactions on Components and Packaging Technologies.

[4]  Yogendra Joshi,et al.  A compact approach to on-chip interconnect heat conduction modeling using the finite element method , 2008 .

[5]  Bartosz Maj,et al.  A structure oriented compact thermal model for multiple heat source ASICs , 2005, Microelectron. J..

[6]  G. Wachutka,et al.  Calculation of the temperature development in electronic systems by convolution integrals , 2000, Sixteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.00CH37068).

[7]  S. Gurrum.  Thermal Modeling and Characterization of Nanoscale Metallic Interconnects , 2006 .

[8]  Gerhard Wachutka,et al.  Rigorous model and network for transient thermal problems , 2002 .

[9]  Bartosz Maj,et al.  Heat propagation in H-bridge smart power chips under switching conditions , 2002 .

[10]  D. Schweitzer,et al.  Thermal transient modeling and experimental validation in the European project PROFIT , 2004 .

[11]  Jing Zhang,et al.  Thermal stresses in 3D IC inter-wafer interconnects , 2005 .

[12]  Gerhard Wachutka,et al.  Time dependent temperature fields calculated using eigenfunctions and eigenvalues of the heat conduction equation , 2001 .

[13]  Clemens J. M. Lasance,et al.  The Use of Time-Dependent Temperature Response Curves for the Generation of (Dynamic) Compact Thermal Models , 2003 .

[14]  J. Z. Zhu,et al.  The finite element method , 1977 .