Random Process Variation in Deep-Submicron CMOS

One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key parameters affecting performance of integrated circuits [1]. Although scaling made controlling extrinsic variability more complex, nonetheless, the most profound reason for the future increase in parameter variability is that the technology is approaching the regime of fundamental randomness in the behavior of silicon structures where device operation must be described as a stochastic process. Electric noise due to the trapping and de-trapping of electrons in lattice defects may result in large current fluctuations, and those may be different for each device within a circuit.

[1]  Noel Menezes,et al.  A “true” electrical cell model for timing, noise, and power grid verification , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[2]  Georges G. E. Gielen,et al.  WATSON: design space boundary exploration and model generation for analog and RFIC design , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Yici Cai,et al.  Statistical Analysis of On-Chip Power Delivery Networks Considering Lognormal Leakage Current Variations With Spatial Correlation , 2008, IEEE Trans. Circuits Syst. I Regul. Pap..

[4]  Andrew R. Brown,et al.  Increase in the random dopant induced threshold fluctuations and lowering in sub-100 nm MOSFETs due to quantum effects: a 3-D density-gradient simulation study , 2001 .

[5]  Anantha Chandrakasan,et al.  Variation-Driven Device Sizing for Minimum Energy Sub-threshold Circuits , 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

[6]  David Blaauw,et al.  A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Jan M. Rabaey,et al.  Ultralow-Power Design in Near-Threshold Region , 2010, Proceedings of the IEEE.

[8]  Costas J. Spanos,et al.  Modeling within-field gate length spatial variation for process-design co-optimization , 2005, SPIE Advanced Lithography.

[9]  I. Postlethwaite,et al.  Truncated balanced realization of a stable non-minimal state-space system , 1987 .

[10]  Murat R. Becer,et al.  Transistor level gate modeling for accurate and fast timing, noise, and power analysis , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[11]  Hakan Yalcin,et al.  Transistor-level timing analysis using embedded simulation , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[12]  Takayasu Sakurai,et al.  Optimization of V/sub DD/ and V/sub TH/ for low-power and high-speed applications , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

[13]  T. T. Soong,et al.  Random differential equations in science and engineering , 1974 .

[14]  Leon O. Chua,et al.  Linear and nonlinear circuits , 1987 .

[15]  James D. Meindl,et al.  Impact of within-die parameter fluctuations on future maximum clock frequency distributions , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[16]  Min Chen,et al.  Fast statistical circuit analysis with finite-point based transistor model , 2007 .

[17]  Lawrence T. Pileggi,et al.  TETA: transistor-level engine for timing analysis , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[18]  Joel R. Phillips,et al.  Poor man's TBR: a simple model reduction scheme , 2004 .

[19]  Ben Taskar,et al.  Learning structured prediction models: a large margin approach , 2005, ICML.

[20]  Václav Hlavác,et al.  Multi-class support vector machine , 2002, Object recognition supported by user interaction for service robots.

[21]  Qin Tang,et al.  RDE-based transistor-level gate simulation for statistical static timing analysis , 2010, Design Automation Conference.

[22]  David G. Chinnery,et al.  Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization , 2003, ISLPED '03.

[23]  Shahin Nazarian,et al.  Statistical logic cell delay analysis using a current-based model , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[24]  A. Asenov,et al.  Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variations , 2002 .

[25]  Mohammed Ismail,et al.  Statistical Modeling for Computer-Aided Design of Mos VLSI Circuits , 1993 .

[26]  Natesan Venkateswaran,et al.  First-Order Incremental Block-Based Statistical Timing Analysis , 2006, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[27]  Qin Tang,et al.  Direct Statistical Simulation of Timing Properties in Sequential Circuits , 2012, PATMOS.

[28]  Noel Menezes,et al.  A nonlinear cell macromodel for digital applications , 2007, ICCAD 2007.

[29]  Sarvesh Bhardwaj,et al.  A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[30]  Zhi-Quan Luo,et al.  Robust gate sizing by geometric programming , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[31]  L. Arnold.  Stochastic Differential Equations: Theory and Applications , 1992 .

[32]  Martin D. F. Wong,et al.  Blade and razor: cell and interconnect delay analysis using current-based models , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[33]  D. Enns.  Model reduction with balanced realizations: An error bound and a frequency weighted generalization , 1984, The 23rd IEEE Conference on Decision and Control.

[34]  Kiyoo Itoh,et al.  Adaptive circuits for the 0.5-V nanoscale CMOS era , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[35]  Keith A. Bowman,et al.  A minimum total power methodology for projecting limits on CMOS GSI , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[36]  Bernabé Linares-Barranco,et al.  On an Efficient CAD Implementation of the Distance Term in Pelgrom's Mismatch Model , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[37]  Takeshi Shima,et al.  Table Look-Up MOSFET Modeling System Using a 2-D Device Simulator and Monotonic Piecewise Cubic Interpolation , 1983, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[38]  Yoav Freund,et al.  Large Margin Classification Using the Perceptron Algorithm , 1998, COLT.

[39]  Luís Miguel Silveira,et al.  Guaranteed passive balancing transformations for model order reduction , 2002, DAC '02.

[40]  Zhuo Feng,et al.  Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[41]  John C. Platt,et al.  Fast training of support vector machines using sequential minimal optimization, advances in kernel methods , 1999 .

[42]  Jaeha Kim,et al.  Stochastic steady-state and AC analyses of mixed-signal systems , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[43]  Michael Orshansky,et al.  An efficient algorithm for statistical minimization of total power under timing yield constraints , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[44]  K. Fernando,et al.  Singular perturbational model reduction of balanced systems , 1982 .

[45]  Sarma B. K. Vrudhula,et al.  Statistical waveform and current source based standard cell models for accurate timing analysis , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[46]  N. P. van der Meijs,et al.  Including higher-order moments of RC interconnections in layout-to-circuit extraction , 1996, Proceedings ED&TC European Design and Test Conference.

[47]  A. Toriumi,et al.  Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET's , 1994 .

[48]  M.J.M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[49]  Michel Loève,et al.  Probability Theory I , 1977 .

[50]  Martin D. F. Wong,et al.  A fast and accurate technique to optimize characterization tables for logic synthesis , 1997, DAC.

[51]  Amir Zjajo,et al.  Statistical delay calculation with Multiple Input Simultaneous Switching , 2011, 2011 IEEE International Conference on IC Design & Technology.

[52]  James F. Epperson,et al.  An Introduction to Numerical Methods and Analysis , 2001 .

[53]  A. Laub,et al.  Generalized eigenproblem algorithms and software for algebraic Riccati equations , 1984, Proceedings of the IEEE.

[54]  Sani R. Nassif,et al.  High Performance CMOS Variability in the 65nm Regime and Beyond , 2006, 2007 IEEE International Electron Devices Meeting.

[55]  Anirudh Devgan.  Accurate device modeling techniques for efficient timing simulation of integrated circuits , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[56]  Qin Tang,et al.  Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[57]  José Pineda de Gyvez,et al.  Body bias driven design synthesis for optimum performance per area , 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

[58]  Harold S. Stone,et al.  A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.

[59]  Jinjun Xiong,et al.  Robust Extraction of Spatial Correlation , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[60]  W. Sansen,et al.  Line edge roughness: characterization, modeling and impact on device behavior , 2002, Digest. International Electron Devices Meeting,.

[61]  Costas J. Spanos,et al.  Modeling within-die spatial correlation effects for process-design co-optimization , 2005, Sixth international symposium on quality electronic design (isqed'05).

[62]  Alex Doboli,et al.  ALAMO: An Improvedσ-Space Based Methodology for Modeling Process Parameter Variations in Analog Circuits , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[63]  Roberto Manduchi,et al.  Independent component analysis of textures , 1999, Proceedings of the Seventh IEEE International Conference on Computer Vision.

[64]  Roland W. Freund,et al.  Efficient linear circuit analysis by Pade´ approximation via the Lanczos process , 1994, EURO-DAC '94.

[65]  Jianwen Zhu,et al.  Transistor-level static timing analysis by piecewise quadratic waveform matching , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[66]  L. Signoracci,et al.  SiSMA: a statistical simulator for mismatch analysis of MOS ICs , 2002, ICCAD 2002.

[67]  Jaijeet S. Roychowdhury,et al.  An efficient, fully nonlinear, variability-aware non-monte-carlo yield estimation procedure with applications to SRAM cells and ring oscillators , 2008, 2008 Asia and South Pacific Design Automation Conference.

[68]  Amir Zjajo,et al.  Analog Automatic Test Pattern Generation for Quasi-Static Structural Test , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[69]  Mircea Grigoriu,et al.  On the spectral representation method in simulation , 1993 .

[70]  M. Safonov,et al.  A Schur method for balanced-truncation model reduction , 1989 .

[71]  Vladimir Stojanovic,et al.  Methods for true power minimization , 2002, ICCAD 2002.

[72]  Bao Liu.  Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[73]  Thomas Hofmann,et al.  Support vector machine learning for interdependent and structured output spaces , 2004, ICML.

[74]  Lawrence T. Pileggi,et al.  PRIMA: passive reduced-order interconnect macromodeling algorithm , 1997, ICCAD 1997.

[75]  Amir Zjajo,et al.  Digitally programmable continuous-time biquad filter in 65-nm CMOS , 2009, 2009 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT).

[76]  B. Moore.  Principal component analysis in linear systems: Controllability, observability, and model reduction , 1981 .

[77]  Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling , 1997, ICCAD 1997.

[78]  A.B. Kahng,et al.  Statistical Gate Level Simulation via Voltage Controlled Current Source Models , 2006, 2006 IEEE International Behavioral Modeling and Simulation Workshop.

[79]  Lawrence T. Pileggi,et al.  TETA: transistor-level waveform evaluation for timing analysis , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[80]  Carl Sechen,et al.  WTA: waveform-based timing analysis for deep submicron circuits , 2002, ICCAD 2002.

[81]  Lawrence T. Pileggi,et al.  Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[82]  Kishore Singhal,et al.  Computer Methods for Circuit Analysis and Design , 1983 .

[83]  Erkki Oja,et al.  Independent component analysis: algorithms and applications , 2000, Neural Networks.

[84]  Noel Menezes,et al.  A multi-port current source model for multiple-input switching effects in CMOS library cells , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[85]  Thilo Penzl,et al.  A Cyclic Low-Rank Smith Method for Large Sparse Lyapunov Equations , 1998, SIAM J. Sci. Comput..

[86]  Massoud Pedram,et al.  A Current Source Model for CMOS Logic Cells Considering Multiple Input Switching and Stack Effect , 2008, 2008 Design, Automation and Test in Europe.

[87]  Peivand F. Tehrani,et al.  Deep sub-micron static timing analysis in presence of crosstalk , 2000, Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525).

[88]  Rafael López-Ahumada,et al.  FASTEST: A Tool for a Complete and Efficient Statistical Evaluation of Analog Circuits. DC Analysis , 2001 .

[89]  Amir Zjajo,et al.  Low-Power Die-Level Process Variation and Temperature Monitors for Yield Analysis and Optimization in Deep-Submicron CMOS , 2012, IEEE Transactions on Instrumentation and Measurement.

[90]  K. Bernstein,et al.  Scaling, power, and the future of CMOS , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[91]  Gene H. Golub,et al.  Matrix computations , 1983 .