750Mb/s 17pJ/b 90nm CMOS (120,75) TS-LDPC Min-Sum based analog decoder

Circuit and IC implementation of a (120, 75) Min-Sum based Turbo-Structured LDPC analog decoder in CMOS 90nm technology is presented. This is the highest throughput and one of the longest codes implemented to date using analog techniques. At a Bit Error Rate of 10-5, the measured performance is within 0.2dB of modeled performance using floating-point arithmetic. The chip was tested at a throughput of 750Mb/s. This improves the throughput of analog decoders by a factor of 57. The power dissipation of the core is 13 mW resulting in 17pJ/b energy efficiency. The core area is 1.38mm2. The fabricated MS-based TS-LDPC analog decoder has BER performance nearly identical to theory without compromising energy efficiency.

[1]  Hsie-Chia Chang,et al.  A 2.37Gb/s 284.8mW rate-compatible (491,3,6) LDPC-CC decoder , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[2]  Vincent C. Gaudet,et al.  Decoder IC with a Configurable Interleaver , 2003 .

[3]  T. Temel.  High-performance current-mode multi-input loser-take-all minimum circuit , 2008 .

[4]  P.G. Gulak,et al.  A 13.3Mb/s 0.35/spl mu/m CMOS analog turbo decoder IC with a configurable interleaver , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[5]  Frank R. Kschischang,et al.  Power Reduction Techniques for LDPC Decoders , 2008, IEEE Journal of Solid-State Circuits.

[6]  A. Neviani,et al.  A 0.35-/spl mu/m CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code , 2005, IEEE Journal of Solid-State Circuits.

[7]  A. R. Abolfazli,et al.  TS-LDPC analog decoding based on the Min-Sum algorithm , 2012, 2012 26th Biennial Symposium on Communications (QBSC).

[8]  Ming Gu,et al.  A 100 pJ/bit, (32,8) CMOS Analog Low-Density Parity-Check Decoder Based on Margin Propagation , 2011, IEEE Journal of Solid-State Circuits.

[9]  C. Plett,et al.  A 0.18-$muhbox m$CMOS Analog Min-Sum Iterative Decoder for a (32,8) Low-Density Parity-Check (LDPC) Code , 2006, IEEE Journal of Solid-State Circuits.

[10]  Hsie-Chia Chang,et al.  A 2.37-Gb/s 284.8 mW Rate-Compatible (491,3,6) LDPC-CC Decoder , 2012, IEEE Journal of Solid-State Circuits.