Testability-based partial scan analysis

In this paper, we present a new method for selecting flip-flops for partial scan. Our method ranks all flip-flops in a circuit based on a sensitivity analysis which estimates the relative improvement in the testability of the circuit as a result of scanning a flip-flop. The testability is an estimate of the fault coverage expected for the circuit and is computed with respect to a given set of target faults. Several cost functions are used to compute testability, taking both structural and logical aspects of the circuit into account. Our results show a good correlation between the computed testability and the actual fault coverage. We give a testability-based estimate on the number of scan flip-flops needed to reach a high fault coverage.

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