DS-CDMA UWB를 위한 6Bit 2.704Gs/s DAC

This paper presents a design of a 6-bit 2.704Gsamples/s D/A converter (DAC) for DS-CDMA UWB transceivers. The proposed DAC was designed with a current steering segmented 4＋2 architecture for high frequency sampling rate. For low glitches, optimized deglitch circuit is adopted for the selection of current sources. The measured integral nonlinearity (INL) is -0.081 LSB and the measured differential nonlinearity (DNL) is -0.065 LSB. The DAC implemented in a 0.13㎛ CMOS technology shows s spurious free dynamic range (SFDR) of 50dB from dc to Nyquist frequency. The prototype DAC consumes 28㎽ for a Nyquist sinusoidal output signal at a 2.704Gsamples/s. The chip has an active area of 0.76㎟