GaN-based MIS-HEMTs: Impact of cascode-mode high temperature source current stress on NBTI shift

This paper reports on the trapping mechanism of GaN-based metal-insulator-semiconductor (MIS) high electron mobility transistors (HEMTs) designed to work in a cascode configuration. We defined a novel stress protocol (High Temperature, Source Current, HTSC) to investigate the degradation processes induced by semi-on state operation. We compare the results of HTSC with those obtained by the standard HTRB (high temperature reverse bias), with the aim of identifying different impact on the RON variation. While HTRB stress results in a strong negative bias/temperature instability (NBTI), under HTSC conditions no significant Vth shift is observed. This result is ascribed to the fact that under HTSC conditions the gate-source voltage difference is significantly smaller than under HTRB, thus having less impact on Vth stability. The technique described in this paper is useful to test the Vth stability of normally-on devices used in cascode configuration.