Smart-MSP: A Self-Adaptive Multiple Starting Point Optimization Approach for Analog Circuit Synthesis
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Xuan Zeng | Changhao Yan | Hengliang Zhu | Dian Zhou | Yishi Yang | Zhaori Bi | Yangfeng Su | Changhao Yan | Xuan Zeng | Dian Zhou | Zhaori Bi | Hengliang Zhu | Yangfeng Su | Yishi Yang | Hengliang Zhu
[1] Fred Glover,et al. Tabu Search - Part II , 1989, INFORMS J. Comput..
[2] Man-Kay Law,et al. A 0.016mm2 144μW three-stage amplifier capable of driving 1-to-15nF capacitive load with >0.95MHz GBW , 2012, 2012 IEEE International Solid-State Circuits Conference.
[3] Rob A. Rutenbar,et al. Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs , 2007, Proceedings of the IEEE.
[4] Stephen P. Boyd,et al. Optimal design of a CMOS op-amp via geometric programming , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[5] Dean Liu,et al. A Framework for Designing Reusable Analog Circuits , 2003 .
[6] Tim Mitchell,et al. A BFGS-SQP method for nonsmooth, nonconvex, constrained optimization and its evaluation using relative minimization profiles , 2017, Optim. Methods Softw..
[7] Hazem M. Abbas,et al. Chameleon ART: a non-optimization based analog design migration framework , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[8] Xuan Zeng,et al. A practical method for auto-design and optimization of DC-DC buck converter , 2013, 2013 IEEE 10th International Conference on ASIC.
[9] Jan Van der Spiegel,et al. GBOPCAD: a synthesis tool for high-performance gain-boosted opamp design , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.
[10] Alex Doboli,et al. Refinement-based synthesis of continuous-time analog filters through successive domain pruning, plateau search, and adaptive sampling , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[11] Mark Fleischer. Simulated annealing: past, present, and future , 1995, WSC '95.
[12] Y. Rahmat-Samii,et al. Particle swarm optimization in electromagnetics , 2004, IEEE Transactions on Antennas and Propagation.
[13] William Gropp,et al. MPICH2: A New Start for MPI Implementations , 2002, PVM/MPI.
[14] Christofer Toumazou,et al. The invention of CMOS amplifiers using genetic programming and current-flow analysis , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[15] Alain Greiner,et al. Analog design for reuse - case study: very low-voltage sigma-delta modulator , 2001, DATE '01.
[16] Georges G. E. Gielen,et al. Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[17] Constantine Caramanis,et al. Enabling efficient analog synthesis by coupling sparse regression and polynomial optimization , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).
[18] Fred W. Glover,et al. Scatter Search and Local Nlp Solvers: A Multistart Framework for Global Optimization , 2006, INFORMS J. Comput..
[19] Alex Doboli,et al. A low-voltage, low-power amplifier created by reasoning-based, systematic topology synthesis , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).
[20] Anne Boomsma,et al. Cross-Validation in Regression and Covariance Structure Analysis , 1992 .
[21] Masakazu Muramatsu,et al. SparsePOP: a Sparse Semidefinite Programming Relaxation of Polynomial Optimization Problems , 2005 .
[22] Xuan Zeng,et al. Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[23] Joel A. Tropp,et al. Signal Recovery From Random Measurements Via Orthogonal Matching Pursuit , 2007, IEEE Transactions on Information Theory.
[24] Mariusz Naumowicz,et al. Technology migration of analogue CMOS circuits using hooke-jeeves algorithm and genetic algorithms in multi-core CPU systems , 2013, Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2013.
[25] Xuan Zeng,et al. FMSSQP: An efficient global optimization tool for the robust design of Rail-to-Rail Op-Amp , 2013, 2013 IEEE 10th International Conference on ASIC.
[26] John L. Bresina,et al. Heuristic-Biased Stochastic Sampling , 1996, AAAI/IAAI, Vol. 1.
[27] Michiel Steyaert,et al. Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[28] Constantine Caramanis,et al. Predictable Equation-Based Analog Optimization Based on Explicit Capture of Modeling Error Statistics , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[29] Holger Dette. A note on some peculiar nonlinear extremal phenomena of the Chebyshev polynomials , 1994 .
[30] Fred W. Glover,et al. Tabu Search - Part I , 1989, INFORMS J. Comput..
[31] Ngai Wong,et al. Analog circuit design by nonconvex polynomial optimization: Two design examples , 2010 .
[32] Masakazu Muramatsu,et al. Sums of Squares and Semidefinite Programming Relaxations for Polynomial Optimization Problems with Structured Sparsity , 2004 .
[33] Surya Ganguli,et al. Identifying and attacking the saddle point problem in high-dimensional non-convex optimization , 2014, NIPS.
[34] Lars Hedrich,et al. Topology synthesis of analog circuits with yield optimization and evaluation using pareto fronts , 2011, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip.
[35] Xuan Zeng,et al. An Efficient Optimization Based Method to Evaluate the DRV of SRAM Cells , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.
[36] Man-Kay Law,et al. A 0.016-mm2 144-µW Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With > 0.95-MHz GBW , 2013, IEEE J. Solid State Circuits.
[37] Rainer Storn,et al. Differential Evolution – A Simple and Efficient Heuristic for global Optimization over Continuous Spaces , 1997, J. Glob. Optim..
[38] Yao-Wen Chang,et al. Recent research development and new challenges in analog layout synthesis , 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).
[39] Xiaola Lin,et al. Analysis of optimal thread pool size , 2000, OPSR.