In this paper, we present a design of the fully differential high-order multi-stage noise shaping (MASH) delta-sigma modulator (DSM). To improve the transmission error, a current feedback method is used in the proposed switched-current feedback memory cell (FMC) to decrease the input impedance. Furthermore, the entire memory cell is designed in a coupled differential replicate (CDR) form to eliminate the clock feedthrough (CFT) error. Note that the DSM is simulated with TSMC 0.18 mum CMOS process technology. And that, the simulation results reveal that the peak signal to noise plus distortion ratio (SNDR) is 83 dB at 10.24 MHz sampling rate with 40 kHz bandwidth, and the power dissipation is 12.3 mW.
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