Modelling and evaluation of substrate noise induced by interconnects

Interconnects have received attention as a source of crosstalk to other interconnects, but have been ignored as a source of substrate noise. The importance of interconnect-induced substrate noise is evaluated in this paper. A known interconnect and substrate model is validated by comparing simulation results to experimental measurements. Based on the validated modelling approach, a complete study considering frequency, geometrical, load and shielding effects is presented. The importance of interconnect-induced substrate noise is demonstrated after observing that, for typically sized interconnects and state-of-the-art speeds, the amount of coupled noise is already comparable to that injected by hundreds of transistors. The need to include high-frequency effects in the model is also discussed, together with accuracy trade-offs.

[1]  Michael B. Steer,et al.  Foundations of Interconnect and Microstrip Design , 2000 .

[2]  T. Sakurai,et al.  Approximation of wiring delay in MOSFET LSI , 1983, IEEE Journal of Solid-State Circuits.

[3]  Maher Kayal,et al.  LAYIN: toward a global solution for parasitic coupling modeling and visualization , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

[4]  Miquel Roca,et al.  Inductance in VLSI interconnection modelling , 1998 .

[5]  G. Gonzalez Microwave Transistor Amplifiers: Analysis and Design , 1984 .

[6]  David J. Allstot,et al.  Verification techniques for substrate coupling and their application to mixed-signal IC design , 1996 .

[7]  M. B. Steer,et al.  Foundations of Interconnect and Microstrip Design: Edwards/Foundations of Interconnect and Microstrip Design , 2000 .

[8]  Robert G. Meyer,et al.  Modeling and analysis of substrate coupling in integrated circuits , 1996 .

[9]  W. R. Eisenstadt,et al.  S-parameter-based IC interconnect transmission line characterization , 1992 .

[10]  J. Briaire,et al.  Principles of substrate crosstalk generation in CMOS circuits , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  J. Ackermann,et al.  Analysis and Design , 1993 .

[12]  Xavier Aragones,et al.  Experimental comparison of substrate noise coupling using different wafer types , 1999 .

[13]  W. R. Eisenstadt,et al.  High-speed VLSI interconnect modeling based on S-parameter measurements , 1993 .

[14]  Robert W. Dutton,et al.  High-frequency characterization of on-chip digital interconnects , 2002, IEEE J. Solid State Circuits.

[15]  G. Matthaei,et al.  Experimental analysis of transmission line parameters in high-speed GaAs digital circuit interconnects , 1991 .