Complex division and square-root using CORDIC

In this paper, we present designs of CORDIC-based fixed-point complex division and square-root FPGA implementations. We optimized the arithmetic of CORDIC unit, complex division and square-root. Then a architecture of CORDIC units based recurrence architecture was proposed. The complex number division and square-root was implement and evaluated on a Altera Stratix II FPGAs, with max frequency up to 180Mhz, and can easily be ported to ASIC implementation. These architecture have good numerical properties and the result is accurate to less than one ulp.

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